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    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics
    1.
    发明授权
    Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
    制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层

    公开(公告)号：US07678625B2

    公开(公告)日：2010-03-16

    申请号：US11962742

    申请日：2007-12-21

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/84

    CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

    摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING CHANNEL LAYERS HAVING IMPROVED DEFECT DENSITY AND SURFACE ROUGHNESS CHARACTERISTICS
    3.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING CHANNEL LAYERS HAVING IMPROVED DEFECT DENSITY AND SURFACE ROUGHNESS CHARACTERISTICS 有权
    制备半导体器件的方法，包括具有改善的缺陷密度和表面粗糙特性的通道层

    公开(公告)号：US20080160726A1

    公开(公告)日：2008-07-03

    申请号：US11962742

    申请日：2007-12-21

    申请人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

    摘要翻译： 制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。 单晶半导体层包括从其表面延伸的突起。 在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。 执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。 可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。 还讨论了制造叠层半导体存储器件的相关方法。

    Methods of forming semiconductor devices
    4.
    发明申请
    Methods of forming semiconductor devices 有权
    形成半导体器件的方法

    公开(公告)号：US20080200007A1

    公开(公告)日：2008-08-21

    申请号：US12070220

    申请日：2008-02-15

    申请人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    发明人： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/3212

    摘要： A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

    摘要翻译： 一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。

    METHOD OF MANUFACTURING A STACK-TYPE SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING A STACK-TYPE SEMICONDUCTOR DEVICE 审中-公开
    制造堆叠型半导体器件的方法

    公开(公告)号：US20080138960A1

    公开(公告)日：2008-06-12

    申请号：US11936965

    申请日：2007-11-08

    申请人： Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Young-Ho Koh ,  Seong-Kyu Yun ,  Jong-Heun Lim

    发明人： Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Young-Ho Koh ,  Seong-Kyu Yun ,  Jong-Heun Lim

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76254 ,  H01L21/3212 ,  H01L21/32139

    摘要： A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow the surface layer to make contact with the insulation layer. The first substrate is partially separated from the second substrate to allow the surface layer to remain on a central portion of the second substrate. A sacrificial layer pattern is then formed on an edge portion of the second substrate having the surface layer. The sacrificial layer pattern and the surface layer are planarized. Thus, the sacrificial layer pattern may reduce damage to the edge portion of the second substrate so that the second substrate may have an improved flatness.

    摘要翻译： 制造堆叠型半导体器件的方法，其中制备第一衬底和第二衬底，使得第一衬底具有表面层，并且第二衬底具有绝缘层。 第一基板和第二基板彼此附接以允许表面层与绝缘层接触。 第一衬底与第二衬底部分地分离以允许表面层保留在第二衬底的中心部分上。 然后在具有表面层的第二基板的边缘部分上形成牺牲层图案。 牺牲层图案和表面层被平坦化。 因此，牺牲层图案可以减小对第二基板的边缘部分的损伤，使得第二基板可以具有改善的平坦度。

    Methods of fabricating a semiconductor device
    6.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20090155991A1

    公开(公告)日：2009-06-18

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Methods of fabricating a semiconductor device
    9.
    发明授权
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08084344B2

    公开(公告)日：2011-12-27

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。