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    FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF
    1.
    发明申请
    FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
    闪存存储器件及其编程方法

    公开(公告)号：US20100008149A1

    公开(公告)日：2010-01-14

    申请号：US12485983

    申请日：2009-06-17

    申请人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

    发明人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3454 ,  G11C16/3459

    摘要： A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed.

    摘要翻译： 一种具有存储单元的闪速存储器件的编程方法，以及执行该方法的闪速存储器件，包括根据加载的数据对所选择的存储器单元进行编程，感测编程的存储器单元的状态，并首先锁定感测的状态，以及确定是否 在确定所选择的存储器单元是否被正确地编程之前，参考所加载的数据和锁存状态，已编程所选存储单元中的程序禁止存储单元。

    FLASH MEMORY DEVICES WITH HIGH DATA TRANSMISSION RATES AND MEMORY SYSTEMS INCLUDING SUCH FLASH MEMORY DEVICES
    5.
    发明申请
    FLASH MEMORY DEVICES WITH HIGH DATA TRANSMISSION RATES AND MEMORY SYSTEMS INCLUDING SUCH FLASH MEMORY DEVICES 有权
    具有高数据传输速率的闪速存储器件和包括这种闪存存储器件的存储器系统

    公开(公告)号：US20120089770A1

    公开(公告)日：2012-04-12

    申请号：US13332904

    申请日：2011-12-21

    申请人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    发明人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    IPC分类号： G06F12/00

    CPC分类号： G06F1/12 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/32

    摘要： A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

    摘要翻译： 闪速存储器件包括存储单元阵列，时钟信号输入端，用于接收指定写入操作模式的信号的输入端，多个数据输入/输出焊盘和数据输入/输出缓冲电路， 时钟信号输入和多个数据输入/输出焊盘。 数据输入/输出缓冲电路被配置为响应于信号的激活而与应用于时钟信号输入的时钟信号同步地通过数据输入/输出焊盘接收要写入存储单元阵列的数据 指定书写操作模式。

    Flash memory devices with high data transmission rates and memory systems including such flash memory devices
    7.
    发明授权
    Flash memory devices with high data transmission rates and memory systems including such flash memory devices 有权
    具有高数据传输速率的闪存设备和包括这种闪存设备的存储器系统

    公开(公告)号：US08464087B2

    公开(公告)日：2013-06-11

    申请号：US13332904

    申请日：2011-12-21

    申请人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    发明人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    IPC分类号： G06F1/12 ,  G11C11/34

    CPC分类号： G06F1/12 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/32

    摘要： A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

    摘要翻译： 闪速存储器件包括存储单元阵列，时钟信号输入端，用于接收指定写入操作模式的信号的输入端，多个数据输入/输出焊盘和数据输入/输出缓冲电路， 时钟信号输入和多个数据输入/输出焊盘。 数据输入/输出缓冲电路被配置为响应于信号的激活而与应用于时钟信号输入的时钟信号同步地通过数据输入/输出焊盘接收要写入存储单元阵列的数据 指定书写操作模式。

    Flash memory devices with high data transmission rates and memory systems including such flash memory devices
    8.
    发明授权
    Flash memory devices with high data transmission rates and memory systems including such flash memory devices 有权
    具有高数据传输速率的闪存设备和包括这种闪存设备的存储器系统

    公开(公告)号：US08286021B2

    公开(公告)日：2012-10-09

    申请号：US11953385

    申请日：2007-12-10

    申请人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    发明人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    IPC分类号： G06F1/12 ,  G11C11/34

    CPC分类号： G06F1/12 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/32

    摘要： A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

    摘要翻译： 闪速存储器件包括存储单元阵列，时钟信号输入端，用于接收指定写入操作模式的信号的输入端，多个数据输入/输出焊盘和数据输入/输出缓冲电路， 时钟信号输入和多个数据输入/输出焊盘。 数据输入/输出缓冲电路被配置为响应于信号的激活而与应用于时钟信号输入的时钟信号同步地通过数据输入/输出焊盘接收要写入存储单元阵列的数据 指定书写操作模式。

    Flash memory device and programming method thereof
    9.
    发明授权
    Flash memory device and programming method thereof 有权
    闪存设备及其编程方法

    公开(公告)号：US08194463B2

    公开(公告)日：2012-06-05

    申请号：US12485983

    申请日：2009-06-17

    申请人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

    发明人： Jong-Hwa Kim ,  Seok-Cheon Kwon ,  Young-Joon Choi

    IPC分类号： G11C16/06 ,  G11C11/34

    CPC分类号： G11C16/3454 ,  G11C16/3459

    摘要： A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed.

    摘要翻译： 一种具有存储单元的闪速存储器件的编程方法，以及执行该方法的闪速存储器件，包括根据加载的数据对所选择的存储器单元进行编程，感测编程的存储器单元的状态，并首先锁定感测的状态，以及确定是否 在确定所选择的存储器单元是否被正确地编程之前，参考所加载的数据和锁存状态，已编程所选存储单元中的程序禁止存储单元。

    Flash Memory Devices with High Data Transmission Rates and Memory Systems Including Such Flash Memory Devices
    10.
    发明申请
    Flash Memory Devices with High Data Transmission Rates and Memory Systems Including Such Flash Memory Devices 有权
    具有高数据传输速率的闪存器件和包括这种闪存器件的存储器系统

    公开(公告)号：US20080141059A1

    公开(公告)日：2008-06-12

    申请号：US11953385

    申请日：2007-12-10

    申请人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    发明人： Yeon-Ho Kim ,  Kyeong-Han Lee ,  Jong-Hwa Kim ,  In-Young Kim ,  Young-Joon Choi ,  Seok-Cheon Kwon

    IPC分类号： G06F1/12 ,  G06F12/02

    CPC分类号： G06F1/12 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/109 ,  G11C16/32

    摘要： A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

    摘要翻译： 闪速存储器件包括存储单元阵列，时钟信号输入端，用于接收指定写入操作模式的信号的输入端，多个数据输入/输出焊盘和数据输入/输出缓冲电路， 时钟信号输入和多个数据输入/输出焊盘。 数据输入/输出缓冲电路被配置为响应于信号的激活而与应用于时钟信号输入的时钟信号同步地通过数据输入/输出焊盘接收要写入存储单元阵列的数据 指定书写操作模式。