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    INTERNAL REFERENCE VOLTAGE GENERATING CIRCUIT FOR REDUCING STANDBY CURRENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    4.
    发明申请
    INTERNAL REFERENCE VOLTAGE GENERATING CIRCUIT FOR REDUCING STANDBY CURRENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    内部基准电压产生电路，用于减少包括其中的待机电流和半导体存储器件

    公开(公告)号：US20070153590A1

    公开(公告)日：2007-07-05

    申请号：US11567826

    申请日：2006-12-07

    申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes, a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuits and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated white the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

    摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：通过电源电压输出所述参考电压的分压电路; 连接到分压电路的一端的下拉驱动器; 以及校准控制电路，其比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果控制下拉驱动器的导通电阻值。 内部参考电压产生电路白色运行，存储器控制器将信号输入到模式寄存器组（MRS）中以使能内部参考电压产生电路，并且MRS的输出信号被激活。

    Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same
    5.
    发明授权
    Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same 有权
    用于降低待机电流的内部参考电压发生电路和包括其的半导体存储器件

    公开(公告)号：US07515487B2

    公开(公告)日：2009-04-07

    申请号：US11567826

    申请日：2006-12-07

    申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

    摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：分压电路，通过电源电压输出基准电压; 连接到分压电路的一端的下拉驱动器; 以及校正控制电路，比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果来控制下拉驱动器的导通电阻值。 内部参考电压产生电路在存储器控制器将信号输入到模式寄存器组（MRS）中的情况下操作，以使能内部基准电压产生电路并且MRS的输出信号被激活。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    7.
    发明授权
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US08310853B2

    公开(公告)日：2012-11-13

    申请号：US12987539

    申请日：2011-01-10

    申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE 有权
    用于半导体存储器件的位线感测放大器的布局结构

    公开(公告)号：US20110103166A1

    公开(公告)日：2011-05-05

    申请号：US12987539

    申请日：2011-01-10

    申请人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    发明人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC分类号： G11C7/06 ,  H03F3/68 ,  H03F3/16 ,  G06F17/50

    CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    9.
    发明授权
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US07869239B2

    公开(公告)日：2011-01-11

    申请号：US12078724

    申请日：2008-04-03

    申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

    Layout structure of bit line sense amplifiers for a semiconductor memory device
    10.
    发明申请
    Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
    用于半导体存储器件的位线读出放大器的布局结构

    公开(公告)号：US20080259668A1

    公开(公告)日：2008-10-23

    申请号：US12078724

    申请日：2008-04-03

    申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

    IPC分类号： G11C5/02 ,  G11C7/06

    CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

    摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

    摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。