公开(公告)号：US06490222B2

公开(公告)日：2002-12-03

申请号：US09875371

申请日：2001-06-05

申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C29/34

摘要： A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

摘要翻译： 本发明的半导体存储器件包括：主解码器，用于响应于第一解码信号，第一预充电信号和第二预充电信号产生字线使能信号; 响应于字线使能信号和第二解码信号的字线驱动信号的字线驱动器; 以及用于响应于命令信号产生第二预充电信号的电路。 响应于第一解码信号和第二预充电信号，字线驱动信号被顺序地去激活，以便减少地面噪声。

公开(公告)号：US06345011B2

公开(公告)日：2002-02-05

申请号：US09758526

申请日：2001-01-10

申请人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

发明人： Jae-Hoon Joo ,  Sang-Seok Kang ,  Jong-Hyun Choi ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/10

摘要： A semiconductor memory device including a plurality of memory blocks having associated with one or more circuit blocks therearound, and a plurality of input/output lines associated with the memory blocks, is disclosed. The input/output lines are divided into at least a first group and a second group. First portions of the input/output lines of the first group are arranged between the adjacent memory blocks while first portions of the input/output lines of the second group are arranged within the circuit blocks around the adjacent memory blocks. Second portions of the input/output lines of the first group are arranged on the circuits blocks around the memory blocks while second portions of the input/output lines of the second group are arranged between the adjacent memory blocks.

摘要翻译： 公开了一种包括与其周围的一个或多个电路块相关联的多个存储块的半导体存储器件，以及与存储器块相关联的多个输入/输出线。 输入/输出线分成至少第一组和第二组。 第一组的输入/输出线的第一部分被布置在相邻的存储块之间，而第二组的输入/输出线的第一部分被布置在邻近的存储块周围的电路块内。 第一组的输入/输出线的第二部分布置在存储块周围的电路块上，而第二组的输入/输出线的第二部分被布置在相邻的存储块之间。

公开(公告)号：US06438042B1

公开(公告)日：2002-08-20

申请号：US09879076

申请日：2001-06-11

申请人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

IPC分类号： G11C700

CPC分类号： G11C11/4094 ,  G11C7/12 ,  H01L27/10897

摘要： A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

摘要翻译： 半导体存储器件包括第一和第二隔离晶体管，用于将一对位线与读出放大器电路电连接/隔离;以及MOS晶体管，其具有与第一和第二隔离晶体管的源极之一共享的源极区域。 MOS晶体管可以用作位线升压电容器。

公开(公告)号：US06396756B1

公开(公告)日：2002-05-28

申请号：US09684190

申请日：2000-10-06

申请人： Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

发明人： Sang-Seok Kang ,  Jae-Hoon Joo ,  Young-Ok Cho

IPC分类号： G11C700

CPC分类号： G11C11/4096

摘要： Integrated circuit memory devices include first and second memory cell arrays, first and second transmission parts between the first and second memory cell arrays, and first and second input/output selection parts between the first and second memory cell arrays, wherein the first transmission part is adjacent the first input/output selection part and wherein the second transmission part is adjacent the second input/output selection part. A transistor in the first transmission part and a transistor in the first input/output selection part can share a first common source/drain region. A transistor in the second transmission part and a transistor in the second input/output selection part also can share a second common source/drain region. First and second input/output selection parts also may be provided between the first and second transmission parts. At least one sense amplifier part may be provided between the first and second input/output selection parts.

摘要翻译： 集成电路存储器件包括第一和第二存储单元阵列，第一和第二存储单元阵列之间的第一和第二传输部分以及第一和第二存储单元阵列之间的第一和第二输入/输出选择部分，其中第一传输部分 邻近第一输入/输出选择部分，并且其中第二传输部分与第二输入/输出选择部分相邻。 第一传输部分中的晶体管和第一输入/输出选择部分中的晶体管可以共享第一公共源极/漏极区域。 第二传输部分中的晶体管和第二输入/输出选择部分中的晶体管也可以共享第二公共源极/漏极区域。 也可以在第一和第二传动部件之间设置第一和第二输入/输出选择部件。 可以在第一和第二输入/输出选择部分之间提供至少一个读出放大器部分。

公开(公告)号：US08477553B2

公开(公告)日：2013-07-02

申请号：US13020450

申请日：2011-02-03

申请人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Sang-Man Byun ,  Jae-Hoon Joo

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  H01H37/76

摘要： Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

摘要翻译： 提供了能够根据操作模式选择性地使用用于逻辑运算的电源电压的熔丝电路。 熔丝电路包括模式产生电路，电源电压选择电路和至少一个保险丝单元。 模式产生电路产生多个模式信号。 电源电压选择电路响应于多个模式信号选择多个电源电压中的一个，并将所选择的电源电压输出到第一节点。 每个熔丝单元耦合在第一节点和地电压之间，并且使用所选择的电源电压作为用于逻辑运算的电源电压。 因此，包括熔丝电路的半导体装置可以精确地测试熔丝的连接状态。

公开(公告)号：US20060132183A1

公开(公告)日：2006-06-22

申请号：US11312953

申请日：2005-12-19

申请人： Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

发明人： Dong-Jin Lim ,  Sang-Seok Kang ,  Byung-Heon Kwak ,  Jae-Hoon Joo ,  Chang-Hag Oh

IPC分类号： H03K19/094

CPC分类号： H03K19/00323

摘要： A semiconductor device that performs stable circuit operations is provided. The device includes: a pull-up driver for pulling up a first node in response to first states of input and control signals; a pull-down driver for pulling down a second node in response to a second state of the input signal; at least one fuse connected between the first node and the second node; a latch for generating an output signal to maintain the state of the second node; and a controller for generating the control signal that is maintained in a first state when the input signal is in the second state, and maintained in the first state and then transitioned to the second state after a predetermined delay time when the input signal is transitioned to the first state. In this construction, even if the fuse is incompletely cut during a process of cutting the fuse, the pull-up driver or the pull-down driver is turned off, thus preventing unnecessary current flow in advance.

摘要翻译： 提供了执行稳定电路操作的半导体器件。 所述装置包括：用于响应于输入和控制信号的第一状态而拉起第一节点的上拉驱动器; 用于响应于所述输入信号的第二状态来拉下第二节点的下拉驱动器; 连接在第一节点和第二节点之间的至少一个熔丝; 用于产生输出信号以保持第二节点的状态的锁存器; 以及控制器，用于当输入信号处于第二状态时产生保持在第一状态的控制信号，并且当输入信号转换到预定的延迟时间后，保持在第一状态，然后转变到第二状态 第一个状态。 在这种结构中，即使在切断保险丝的过程中保险丝不完全切断，则上拉驱动器或下拉驱动器被关闭，从而防止事先不必要的电流流动。

公开(公告)号：US06909654B2

公开(公告)日：2005-06-21

申请号：US10633562

申请日：2003-08-05

申请人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

发明人： Jae-Hoon Joo ,  Jin-Seok Lee ,  Sang-Seok Kang ,  Kyu-Chan Lee ,  Byung-Heon Kwak ,  Byung-Chul Kim

IPC分类号： H01L27/108 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  H01L21/8242 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C2207/2227

摘要： A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

摘要翻译： 半导体存储器件的位线预充电电路包括连接在一对位线之间的预充电电路，用于响应于预充电控制信号和预充电电压发射来对该对位线进行预充电 电路，用于响应于预充电控制信号将预充电电压发送到预充电电路。 当在字线和一对位线之间形成短路时，可以防止预充电电压产生线中的电压降，并且还可以通过防止在半导体存储器件的待机操作期间的电流消耗 电流从一对位线流向预充电电压产生线。

公开(公告)号：US06111457A

公开(公告)日：2000-08-29

申请号：US44382

申请日：1998-03-18

申请人： Jong-Hyoung Lim ,  Sang-Seok Kang ,  Jae-Hoon Joo ,  Chang-Joo Choi

发明人： Jong-Hyoung Lim ,  Sang-Seok Kang ,  Jae-Hoon Joo ,  Chang-Joo Choi

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/02

CPC分类号： G05F1/465

摘要： An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.

摘要翻译： 用于半导体器件的内部电源电路包括用于将内部电压钳位到恒定电平的钳位电路。 被钳位的内部电压通过输出节点分配给半导体器件的内部电路。 当内部电压由于开路现象而由于内部电源电路中的噪声而瞬间上升时，内部电压的上升通过钳位电路放电，从而将内部电压保持在恒定值。 钳位电路包括用于对输出节点放电的第一晶体管和用于在第一晶体管的栅极处产生充电电压的二极管连接的晶体管。 二极管连接晶体管的阈值电压优选等于或低于第一晶体管的阈值电压。

公开(公告)号：US06658612B1

公开(公告)日：2003-12-02

申请号：US09550944

申请日：2000-04-17

申请人： Cheol-Hong Park ,  Sang-Seok Kang ,  Jong-Hyun Choi

发明人： Cheol-Hong Park ,  Sang-Seok Kang ,  Jong-Hyun Choi

IPC分类号： G01R3128

CPC分类号： G11C29/46 ,  G01R31/31813 ,  G11C2029/5004

摘要： A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.

摘要翻译： 半导体器件的信号发生电路包括用于接收各个编码输入信号的n个输入测试引脚。 输入信号中的至少一个以多于两个可能的级别编码，例如3级或4级。 该装置还包括一个指示器I / O信号发生器，每个发生器分别与相关的输入测试引脚相连。 每个指示信号发生器响应于由其相关输入测试引脚接收到的编码输入信号产生两电平指示信号。 解码器接收指示信号以产生解码信号，并且模式选择电路响应于模式设置信号产生具有解码信号的模式选择信号。 当输入测试信号为普通低电平时，指示信号发生器输出常规信号，当输入测试信号为普通高电平时输入控制信号，当输入测试信号为超高电平时，输出高电平信号。 如果使用三个以上的电平，指示信号发生器进一步产生这些较高值的相应信号。

公开(公告)号：US08441877B2

公开(公告)日：2013-05-14

申请号：US12731749

申请日：2010-03-25

申请人： Jong-Hyun Choi ,  Sang-Seok Kang

发明人： Jong-Hyun Choi ,  Sang-Seok Kang

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。 控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。 第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。 还讨论了相关的操作方法。