公开(公告)号：US09165893B2

公开(公告)日：2015-10-20

申请号：US13229193

申请日：2011-09-09

申请人： Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

发明人： Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC分类号： H04B5/00 ,  H01L23/64 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

摘要翻译： 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US08853854B2

公开(公告)日：2014-10-07

申请号：US13221494

申请日：2011-08-30

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

摘要： A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.

摘要翻译： 半导体封装可以包括封装衬底，第一半导体芯片和第二半导体芯片。 第一半导体芯片可以布置在封装衬底上。 第一半导体芯片可以具有电连接到封装基板的插头和布置在插头周围的至少一个绝缘孔。 第二半导体芯片可以布置在第一半导体芯片上。 第二半导体芯片可以电连接到插头。 因此，绝缘孔和绝缘构件可以确保插头和第一半导体芯片之间以及插头之间的电隔离。

公开(公告)号：US08723315B2

公开(公告)日：2014-05-13

申请号：US13470572

申请日：2012-05-14

申请人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

发明人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

摘要： A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

摘要翻译： 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US08633579B2

公开(公告)日：2014-01-21

申请号：US13208455

申请日：2011-08-12

申请人： Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

发明人： Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC分类号： H01L23/02

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

摘要： A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

摘要翻译： 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US20100090326A1

公开(公告)日：2010-04-15

申请号：US12588382

申请日：2009-10-14

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

摘要翻译： 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

公开(公告)号：US20080289177A1

公开(公告)日：2008-11-27

申请号：US12126364

申请日：2008-05-23

申请人： Jong-Joo Lee ,  Soon-Yong Hur

发明人： Jong-Joo Lee ,  Soon-Yong Hur

IPC分类号： H05K3/02

CPC分类号： H05K3/242 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/064 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a circuit board, a semiconductor package including the circuit board, a method of fabricating the circuit board, and a method of fabricating the semiconductor package. The method of fabricating the circuit board includes: forming at least one pair of rows of first bonding pads arranged on a base substrate in a first direction, and a first central plating line formed between the rows of first bonding pads to commonly connect with the rows of first bonding pads; forming an electroplating layer on the first bonding pads; and exposing the base substrate by removing the first central plating line.

摘要翻译： 提供了一种电路板，包括电路板的半导体封装，制造电路板的方法以及制造半导体封装的方法。 制造电路板的方法包括：在第一方向上形成布置在基底基板上的至少一对第一接合焊盘列，以及形成在第一接合焊盘行之间的第一中心电镀线，以与行共同连接 的第一粘接垫; 在所述第一接合焊盘上形成电镀层; 并且通过去除第一中心电镀线来暴露基底。

公开(公告)号：US07131847B2

公开(公告)日：2006-11-07

申请号：US11001182

申请日：2004-12-02

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01R12/00 ,  H05K1/00

CPC分类号： H01R13/2485 ,  G01R1/0466 ,  G01R1/0491 ,  H01R2201/20

摘要： A test apparatus may include a test socket having socket pins with a standard configuration. An intermediate connection board may be interposed between the test socket and a package that has solder balls with a non-standard configuration. The intermediate connection board may have contact balls and contact pads. The contact balls may be arranged in a configuration that is compatible with the standard socket pin configuration, and the contact pads may be arranged in a configuration that is compatible with the non-standard solder ball configuration.

摘要翻译： 测试装置可以包括具有标准配置的插座引脚的测试插座。 中间连接板可以插入在测试插座和具有非标准配置的焊球的封装之间。 中间连接板可以具有接触球和接触垫。 接触球可以布置成与标准插座销配置兼容的配置，并且接触焊盘可以布置成与非标准焊球配置兼容的配置。

公开(公告)号：US20060220215A1

公开(公告)日：2006-10-05

申请号：US11378899

申请日：2006-03-17

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

公开(公告)号：US20050260868A1

公开(公告)日：2005-11-24

申请号：US11001182

申请日：2004-12-02

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L21/66 ,  H01R12/00 ,  H01R13/24

CPC分类号： H01R13/2485 ,  G01R1/0466 ,  G01R1/0491 ,  H01R2201/20

摘要： A test apparatus may include a test socket having socket pins with a standard configuration. An intermediate connection board may be interposed between the test socket and a package that has solder balls with a non-standard configuration. The intermediate connection board may have contact balls and contact pads. The contact balls may be arranged in a configuration that is compatible with the standard socket pin configuration, and the contact pads may be arranged in a configuration that is compatible with the non-standard solder ball configuration.

摘要翻译： 测试装置可以包括具有标准配置的插座引脚的测试插座。 中间连接板可以插入在测试插座和具有非标准配置的焊球的封装之间。 中间连接板可以具有接触球和接触垫。 接触球可以布置成与标准插座销配置兼容的配置，并且接触焊盘可以布置成与非标准焊球配置兼容的配置。

公开(公告)号：US20130161830A1

公开(公告)日：2013-06-27

申请号：US13775580

申请日：2013-02-25

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.