利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.031 秒)

    Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same
    4.
    发明授权
    Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same 有权
    集成电路电容器，其中包含结晶抑制区域的复合电介质层及其形成方法

    公开(公告)号：US08344439B2

    公开(公告)日：2013-01-01

    申请号：US13171163

    申请日：2011-06-28

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    IPC分类号： H01L29/94

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

    Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same
    5.
    发明申请
    Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same 有权
    具有复合介质层的集成电路电容器，其中包含结晶抑制区域和形成方法

    公开(公告)号：US20100187655A1

    公开(公告)日：2010-07-29

    申请号：US12754713

    申请日：2010-04-06

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    IPC分类号： H01L29/92

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

    Capacitors having composite dielectric layers containing crystallization inhibiting regions
    6.
    发明授权
    Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
    具有包含结晶抑制区域的复合电介质层的电容器

    公开(公告)号：US07973352B2

    公开(公告)日：2011-07-05

    申请号：US12754713

    申请日：2010-04-06

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    IPC分类号： H01L29/94

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

    Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions
    7.
    发明授权
    Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
    集成电路电容器，其中包含结晶抑制区的复合介电层

    公开(公告)号：US07723770B2

    公开(公告)日：2010-05-25

    申请号：US11210332

    申请日：2005-08-24

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

    Capacitors and methods of fabricating the same
    8.
    发明申请
    Capacitors and methods of fabricating the same 审中-公开
    电容器及其制造方法

    公开(公告)号：US20070236863A1

    公开(公告)日：2007-10-11

    申请号：US11486065

    申请日：2006-07-14

    申请人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

    发明人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

    IPC分类号： H01G4/06 ,  H01G7/00

    CPC分类号： H01G4/10 ,  H01G4/33 ,  Y10T29/435

    摘要： A capacitor may have a pre-treatment layer formed on a lower electrode, reaction to a dielectric layer and/or deterioration of capacitor characteristics may be suppressed. At least part of the dielectric layer may be oxidized or nitridized after being oxidized, and increases in leakage current may be suppressed. In a method of fabricating a capacitor, a plasma treatment performed before and after the forming of the dielectric layer within the batch-type equipment may cause retention time between the plasma treatment and the deposition of the dielectric layer to be the same or substantially the same for each wafer and/or capacitors may show smaller variations in layer characteristics between wafers.

    摘要翻译： 电容器可以具有形成在下电极上的预处理层，对电介质层的反应和/或电容器特性的劣化被抑制。 电介质层的至少一部分可以在被氧化后被氧化或氮化，并且可以抑制漏电流的增加。 在制造电容器的方法中，在分批式设备中形成电介质层之前和之后执行的等离子体处理可能导致等离子体处理和介电层沉积之间的保持时间相同或基本相同 对于每个晶片和/或电容器可以在晶片之间的层特性中显示较小的变化。

    Semiconductor Device and Method of Fabricating the Same
    10.
    发明申请
    Semiconductor Device and Method of Fabricating the Same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090309187A1

    公开(公告)日：2009-12-17

    申请号：US12544500

    申请日：2009-08-20

    申请人： Jae-hyoung Choi ,  Cha-young Yoo ,  Jong-cheol Lee ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Hoon-sang Choi ,  Se-hoon Oh ,  Se-hwi Cho

    发明人： Jae-hyoung Choi ,  Cha-young Yoo ,  Jong-cheol Lee ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Hoon-sang Choi ,  Se-hoon Oh ,  Se-hwi Cho

    IPC分类号： H01L29/92 ,  H01G4/06

    CPC分类号： H01L28/40 ,  H01L27/10852 ,  H01L28/91

    摘要： Provided is a semiconductor device including a multi-layer dielectric structure and a method of fabricating the semiconductor device. According to one example embodiment, the semiconductor device includes a capacitor comprising: first and second electrodes facing each other; at least one first dielectric layer that is disposed between the first and second electrodes, the at least one first dielectric layer comprising a first high-k dielectric layer doped with silicon; and at least one second dielectric layer that is disposed between the at least one first dielectric layer and any of the first and second electrodes, the at least one second dielectric layer having a higher crystallization temperature than that of the first dielectric layer.

    摘要翻译： 提供了包括多层电介质结构的半导体器件和制造该半导体器件的方法。 根据一个示例性实施例，半导体器件包括电容器，包括：彼此面对的第一和第二电极; 设置在所述第一和第二电极之间的至少一个第一介电层，所述至少一个第一介电层包括掺杂有硅的第一高k电介质层; 以及设置在所述至少一个第一介电层和所述第一和第二电极中的任一个之间的至少一个第二电介质层，所述至少一个第二电介质层具有比所述第一介电层的结晶温度更高的结晶温度。