公开(公告)号：US10181476B2

公开(公告)日：2019-01-15

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US20160293627A1

公开(公告)日：2016-10-06

申请号：US15087127

申请日：2016-03-31

申请人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

发明人： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L27/11565

摘要： Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

摘要翻译： 提供半导体存储器件及其制造方法。 该装置可以包括二维布置在基板上并从基板垂直延伸的垂直通道结构。 该装置还可以包括在垂直通道结构上的位线，并且每个位线可以共同连接到沿第一方向布置的垂直通道结构。 该装置还可以包括在与第一方向相交的第二方向上在垂直通道结构之间延伸的公共源极线和与位线设置在相同垂直电平并将公共源极线彼此电连接的源极捆扎线 。