利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

35 条记录 (耗时 0.048 秒)

    Carrier for test, burn-in, and first level packaging
    3.
    发明授权
    Carrier for test, burn-in, and first level packaging 失效
    用于测试，老化和一级包装的载体

    公开(公告)号：US07132841B1

    公开(公告)日：2006-11-07

    申请号：US09588617

    申请日：2000-06-06

    申请人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    发明人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    IPC分类号： G01R31/26 ,  G01R31/28

    CPC分类号： G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.

    摘要翻译： 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。 载体由柔性材料形成。 它也可以由印刷电路板材料形成。 柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

    Carrier for test, burn-in, and first level packaging
    4.
    发明授权
    Carrier for test, burn-in, and first level packaging 失效
    用于测试，老化和一级包装的载体

    公开(公告)号：US07394268B2

    公开(公告)日：2008-07-01

    申请号：US11531140

    申请日：2006-09-12

    申请人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    发明人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

    摘要翻译： 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

    Structures for wafer level test and burn-in
    5.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06426904B2

    公开(公告)日：2002-07-30

    申请号：US09803500

    申请日：2001-03-09

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Structures for wafer level test and burn-in
    6.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06233184B1

    公开(公告)日：2001-05-15

    申请号：US09191954

    申请日：1998-11-13

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Fabrication processes for monolithic electronic modules
    8.
    发明授权
    Fabrication processes for monolithic electronic modules 失效
    单片电子模块的制造工艺

    公开(公告)号：US5517754A

    公开(公告)日：1996-05-21

    申请号：US252794

    申请日：1994-06-02

    申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

    发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

    IPC分类号： H01L21/28 ,  H01L21/98 ,  H01L25/065 ,  H05K3/34

    CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  Y10S269/903 ,  Y10S269/909 ,  Y10S428/914 ,  Y10T29/49124 ,  Y10T29/49144 ,  Y10T428/14 ,  Y10T428/1438 ,  Y10T428/1481 ,  Y10T428/24942

    摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

    摘要翻译： 本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。 每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。 该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。 多个工件在电子模块之间的堆叠内交错。 每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。 该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。 因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。