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    Isolation in CMOSFET devices utilizing buried air bags
    1.
    发明授权
    Isolation in CMOSFET devices utilizing buried air bags 有权
    使用埋入式气囊的CMOSFET器件中的隔离

    公开(公告)号：US08395217B1

    公开(公告)日：2013-03-12

    申请号：US13283031

    申请日：2011-10-27

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Pranita Kulkarni ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/76289 ,  H01L21/823878 ,  H01L27/1203

    摘要： A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

    摘要翻译： 提供了具有隔离区域的半导体器件结构及其制造方法。 半导体器件结构包括绝缘体上硅（SOI）衬底。 在SOI衬底上形成多个栅极。 半导体器件结构还包括形成在多个栅极中的每一个之间的具有侧壁的沟槽。 半导体器件结构还包括形成在沟槽中的外延横向生长层。 外延横向生长层从沟槽的相对侧壁横向生长，使得外延横向生长层包围延伸到SOI衬底中的沟槽的一部分。 外延横向生长层以这样的方式形成，使得其包括覆盖SOI衬底的掩埋介电层的气隙区域。

    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
    4.
    发明申请
    REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD 有权
    SOI结构和方法中减少的角膜泄漏

    公开(公告)号：US20110291169A1

    公开(公告)日：2011-12-01

    申请号：US12791372

    申请日：2010-06-01

    申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L27/12 ,  H01L21/86 ,  H01L29/78

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

    摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

    摘要翻译： 通过在沟槽中提供衬垫，切割有源半导体层中的导电沟道区域，蚀刻导电沟道的侧面，拐角和/或底部，其中底切暴露半导体材料来提供用于减少晶体管泄漏的复古掺杂的结构替代方案 在有源层中，用绝缘体代替导电沟道的去除部分。 传导通道的这种整形增加了相邻电路元件的距离，如果充电，电荷可能会导致电压并导致导通通道区域中的反向通道阈值的变化并且减小了通道的横截面积 通道的传导不能很好地控制; 这两种效应显着降低了晶体管的泄漏。

    Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal
    5.
    发明授权
    Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal 失效
    使用分层牺牲层去除形成用于高纵横比沟槽的植入板

    公开(公告)号：US08232162B2

    公开(公告)日：2012-07-31

    申请号：US12880419

    申请日：2010-09-13

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L27/1087

    摘要： A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.

    摘要翻译： 形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。 通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。 牺牲填充材料形成在掩模层上并进入深沟槽中。 牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。 牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区 掺杂区域彼此邻接。

    Method to reduce threshold voltage variability with through gate well implant
    6.
    发明授权
    Method to reduce threshold voltage variability with through gate well implant 失效
    通过栅极井注入降低阈值电压变化的方法

    公开(公告)号：US08536649B2

    公开(公告)日：2013-09-17

    申请号：US13608860

    申请日：2012-09-10

    申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

    摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

    摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

    Method to reduce threshold voltage variability with through gate well implant
    7.
    发明授权
    Method to reduce threshold voltage variability with through gate well implant 有权
    通过栅极井注入降低阈值电压变化的方法

    公开(公告)号：US08298884B2

    公开(公告)日：2012-10-30

    申请号：US12862048

    申请日：2010-08-24

    申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

    摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

    摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT
    9.
    发明申请
    METHOD TO REDUCE THRESHOLD VOLTAGE VARIABILITY WITH THROUGH GATE WELL IMPLANT 失效
    通过门式井口植入降低阈值电压变化的方法

    公开(公告)号：US20120326233A1

    公开(公告)日：2012-12-27

    申请号：US13608860

    申请日：2012-09-10

    申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

    摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

    摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部内。

    Junction butting on SOI by raised epitaxial structure and method
    10.
    发明授权
    Junction butting on SOI by raised epitaxial structure and method 有权
    通过凸起的外延结构和方法在SOI上的接合

    公开(公告)号：US09059248B2

    公开(公告)日：2015-06-16

    申请号：US13369382

    申请日：2012-02-09

    申请人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

    发明人： Joseph Ervin ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

    摘要翻译： 一种形成半导体器件的方法，包括通过去除绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的部分，在栅极结构的相对侧上形成阱沟，其中阱沟的基极由 SOI衬底的掩埋介电层的表面和阱沟的侧壁由SOI层的剩余部分提供。 在阱沟的底部形成介电填充材料，其中介质填充材料与阱沟槽的侧壁和提供阱沟的基底的掩埋介电层的表面的至少一部分接触。 在原位掺杂的外延半导体材料的阱沟中形成源极区和漏极区。