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    Silicon carbide inversion channel mosfets
    4.
    发明授权
    Silicon carbide inversion channel mosfets 有权

    公开(公告)号：US06653659B2

    公开(公告)日：2003-11-25

    申请号：US10165400

    申请日：2002-06-07

    申请人： Sei-Hyung Ryu ,  Joseph J. Sumakeris ,  Anant K. Agarwal ,  Ranbir Singh

    发明人： Sei-Hyung Ryu ,  Joseph J. Sumakeris ,  Anant K. Agarwal ,  Ranbir Singh

    IPC分类号： H01L310312

    CPC分类号： H01L29/7802 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  Y10S438/931

    摘要： Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed-over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate. Thus, a silicon carbide power device may be formed without the need for a p-type implant.

    Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation
    5.
    发明授权
    Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation 有权
    制造碳化硅反转通道器件的方法，无需使用P型注入

    公开(公告)号：US06429041B1

    公开(公告)日：2002-08-06

    申请号：US09615386

    申请日：2000-07-13

    申请人： Sei-Hyung Ryu ,  Joseph J. Sumakeris ,  Anant K. Agarwal ,  Ranbir Singh

    发明人： Sei-Hyung Ryu ,  Joseph J. Sumakeris ,  Anant K. Agarwal ,  Ranbir Singh

    IPC分类号： H01L2100

    CPC分类号： H01L29/7802 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  Y10S438/931

    摘要： Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate. Thus, a silicon carbide power device may be formed without the need for a p-type implant.

    摘要翻译： 通过在n型碳化硅衬底上形成第一p型碳化硅外延层来提供碳化硅器件和制造碳化硅器件的方法。 形成n型碳化硅的至少一个第一区域延伸穿过第一p型碳化硅外延层和n型碳化硅衬底，以便在第一p型碳化硅中提供至少一个沟道区 外延层。 n型碳化硅的至少一个第二区域也与n型碳化硅的第一区相邻并间隔开地形成。 在n型碳化硅的第一区域和n型碳化硅的第二区域的至少一部分上形成栅极电介质。 在栅极电介质上形成栅极接触。 还形成第一接触以接触p型外延层和n型碳化硅的第二区域的一部分。 在基板上也形成第二接触。 因此，可以形成碳化硅功率器件，而不需要p型植入物。

    Power switching transistors
    6.
    发明授权
    Power switching transistors 有权
    电源开关晶体管

    公开(公告)号：US07982239B2

    公开(公告)日：2011-07-19

    申请号：US11808915

    申请日：2007-06-13

    申请人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

    发明人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

    IPC分类号： H01L29/47

    CPC分类号： H01L27/098 ,  H01L21/8232 ,  H01L27/0727 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/872

    摘要： In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

    摘要翻译： 在一个实施例中，集成半导体器件包括具有源极的第一垂直结型场效应晶体管（VJFET）和设置在第一VJFET源的每一侧上的栅极和具有源极的第二VJFET晶体管，栅极设置在 第二VJFET源的每一侧。 第一VJFET的至少一个栅极通过沟道与第二VJFET的至少一个栅极分离。 集成半导体器件还包括位于第一和第二VJFET之间的结栅势垒肖特基（JBS）二极管。 JBS二极管包括形成与沟道的整流接触的金属接触和与第一和第二VJFET的至少一个栅极的非整流接触，并且金属接触是JBS二极管的阳极。 第一电连接将第一VJFET的栅极，第二VJFET的栅极和JBS二极管的阳极连接到公共栅电极，并且第二电连接将第一VJFET的源极和第二VJFET的源极连接 到共同的源电极。

    Method, apparatus, material, and system of using a high gain avalanche photodetector transistor
    7.
    发明授权
    Method, apparatus, material, and system of using a high gain avalanche photodetector transistor 有权
    使用高增益雪崩光电探测器晶体管的方法，装置，材料和系统

    公开(公告)号：US07843030B2

    公开(公告)日：2010-11-30

    申请号：US11689524

    申请日：2007-03-22

    申请人： Ranbir Singh

    发明人： Ranbir Singh

    IPC分类号： H01L31/101

    CPC分类号： H01L31/107 ,  H01L27/1446 ,  H01L31/1105

    摘要： Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.

    摘要翻译： 在这里，我们展示了使用半导体材料的光电探测器的新材料/结构。 例如，我们将可调谐雪崩宽基极晶体管作为光电检测器。 特别地，作为实例给出了SiC，GaN，AlN，Si和金刚石材料。 实现了最佳光电探测器所需的性能。 在结构和材料方面讨论了不同的变化。

    METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
    8.
    发明申请
    METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE 审中-公开
    降低SiGe双极器件中硼孔渗透的方法

    公开(公告)号：US20090050977A1

    公开(公告)日：2009-02-26

    申请号：US12256677

    申请日：2008-10-23

    申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

    IPC分类号： H01L27/06

    CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

    摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

    摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

    DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT
    9.
    发明申请
    DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT 有权
    消除由威盛引起的金属偏差的设备和方法

    公开(公告)号：US20070190803A1

    公开(公告)日：2007-08-16

    申请号：US11738050

    申请日：2007-04-20

    申请人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

    发明人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02063 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76831 ,  Y10S438/963

    摘要： The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.

    摘要翻译： 本发明提供了可以用于集成电路中的互连。 互连包括位于衬底上的金属线，位于金属线上方的电介质层和位于电介质层中的互连，其包括位于金属线上的着陆部分和位于金属线的至少一部分上的非上限部分 金属线的侧边。 至少部分地用聚合物填充未上敷的部分，并且所述着陆部分基本上填充有导电材料。 还提供了用于制造互连的方法。

    Robust shallow trench isolation structures and a method for forming shallow trench isolation structures
    10.
    发明申请
    Robust shallow trench isolation structures and a method for forming shallow trench isolation structures 失效
    坚固的浅沟槽隔离结构和形成浅沟槽隔离结构的方法

    公开(公告)号：US20070152294A1

    公开(公告)日：2007-07-05

    申请号：US11321206

    申请日：2005-12-29

    申请人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

    发明人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

    IPC分类号： H01L29/00 ,  H01L21/762

    CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

    摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

    摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。