利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.027 秒)

    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR
    1.
    发明申请
    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
    热控制的金属电阻器

    公开(公告)号：US20120146186A1

    公开(公告)日：2012-06-14

    申请号：US12962722

    申请日：2010-12-08

    申请人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

    摘要翻译： 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

    Thermally controlled refractory metal resistor
    2.
    发明授权
    Thermally controlled refractory metal resistor 有权
    耐热耐火金属电阻

    公开(公告)号：US08592947B2

    公开(公告)日：2013-11-26

    申请号：US12962722

    申请日：2010-12-08

    申请人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/36

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

    摘要翻译： 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

    IC interconnect for high current
    4.
    发明授权
    IC interconnect for high current 有权
    IC互连用于高电流

    公开(公告)号：US08089160B2

    公开(公告)日：2012-01-03

    申请号：US11954866

    申请日：2007-12-12

    申请人： Ping-Chuan Wang ,  Kimball M. Watson ,  Kai Xiu

    发明人： Ping-Chuan Wang ,  Kimball M. Watson ,  Kai Xiu

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An IC interconnect according to one embodiment includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to a top portion of the first via; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at a bottom end and to a metal power line at a top end thereof, wherein the first via is coupled to a first end of the buffer metal segment and the plurality of second vias are coupled to a second end of the buffer metal segment, such that the first via is horizontally off-set from all of the plurality of second vias, wherein the butter metal segment is substantially shorter in length than the metal power line.

    摘要翻译： 根据一个实施例的IC互连包括位于电介质中并且在一端耦合到高电流器件的第一通孔; 位于电介质中并耦合到第一通孔的顶部的缓冲金属段; 以及多个第二通孔，其位于电介质中并在底端处连接到缓冲金属段，并在其顶端处连接到金属电源线，其中第一通孔耦合到缓冲金属段的第一端，并且 多个第二通孔耦合到缓冲金属段的第二端，使得第一通孔与所有多个第二通孔水平偏移，其中黄金金属段的长度短于金属电源线 。

    IC INTERCONNECT FOR HIGH CURRENT
    5.
    发明申请
    IC INTERCONNECT FOR HIGH CURRENT 有权
    IC互连高电流

    公开(公告)号：US20090152724A1

    公开(公告)日：2009-06-18

    申请号：US11954866

    申请日：2007-12-12

    申请人： Ping-Chuan Wang ,  Kimball M. Watson ,  Kai Xiu

    发明人： Ping-Chuan Wang ,  Kimball M. Watson ,  Kai Xiu

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line.

    摘要翻译： 公开了用于大电流器件的IC互连，其设计结构和方法。 IC互连的一个实施例包括位于电介质中的第一通孔，并在一端连接到高电流装置; 位于电介质中并在其另一端耦合到第一通孔的缓冲金属段; 以及多个第二通孔，其位于电介质中并且在一端处连接到缓冲金属段，并且在另一端处连接到金属电源线，其中所述缓冲金属段的长度短于金属电源线。

    In-line depth measurement for thru silicon via
    8.
    发明授权
    In-line depth measurement for thru silicon via 有权
    通过硅通孔的在线深度测量

    公开(公告)号：US07904273B2

    公开(公告)日：2011-03-08

    申请号：US12371724

    申请日：2009-02-16

    申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    IPC分类号： G06F19/00

    CPC分类号： H01L22/34 ,  H01L2924/3011

    摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

    摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

    DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    9.
    发明申请
    DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 有权
    设计结构包括用于半导体器件中的横向电流承载能力改进的手段

    公开(公告)号：US20090106726A1

    公开(公告)日：2009-04-23

    申请号：US11873711

    申请日：2007-10-17

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    10.
    发明申请
    METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 失效
    用于半导体器件中的横向电流承载能力改进的方法

    公开(公告)号：US20080122096A1

    公开(公告)日：2008-05-29

    申请号：US11460314

    申请日：2006-07-27

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。