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    Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure
    7.
    发明授权
    Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure 有权
    结合了多个氮化物层以提高远离器件的散热的半导体结构和形成该结构的方法

    公开(公告)号：US08053870B2

    公开(公告)日：2011-11-08

    申请号：US12638004

    申请日：2009-12-15

    申请人： Brent A. Anderson ,  Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison

    发明人： Brent A. Anderson ,  Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L23/58

    CPC分类号： H01L23/53295 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L2224/18

    摘要： Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation.

    摘要翻译： 公开了一种半导体结构的实施例，该半导体结构包括层叠在器件的中心区域和覆盖氧化物层之间的多个氮化物层。 这些氮化物层比覆盖氧化物层更具有导热性，因此提供远离器件的改进的散热。 还公开了在其它器件的标准处理期间结合形成下列氮化物层的方法的一种方法的实施例：氮化物硬掩模层（OP层），“牺牲”氮化物层（SMT层 ），拉伸氮化物层（WN层）和/或压缩氮化物层（WP层）。 可选地，实施例还包括不完全接触，其将覆盖氧化物层延伸到一个或多个氮化物层中，而不接触该器件，以进一步改善散热。

    Use of contacts to create differential stresses on devices
    8.
    发明授权
    Use of contacts to create differential stresses on devices 有权
    使用触点在器件上产生差分应力

    公开(公告)号：US08815671B2

    公开(公告)日：2014-08-26

    申请号：US12892474

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
    9.
    发明申请
    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
    使用联系人创建设备上的差别应力

    公开(公告)号：US20120074502A1

    公开(公告)日：2012-03-29

    申请号：US12892474

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L25/11 ,  H01L21/77

    CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。 本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。 在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。 在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit
    10.
    发明授权
    Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit 失效
    使用绝缘体上半导体衬底制造的有源器件的器件结构和用于射频集成电路的设计结构

    公开(公告)号：US07709926B2

    公开(公告)日：2010-05-04

    申请号：US12108924

    申请日：2008-04-24

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7436 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

    摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

    摘要翻译： 用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。 器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域 比第一深度，以及半导体层中的第一掺杂区域。 第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。 装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。