公开(公告)号：US08907691B2

公开(公告)日：2014-12-09

申请号：US12490729

申请日：2009-06-24

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G01R31/303 ,  G01R31/28

CPC classification number: G01R31/2875 ,  G01R31/303

Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.

Abstract translation: 提供了一种使用热感应噪声分析测试集成电路（IC）的系统和方法。 该方法提供IC芯片并且为IC芯片提供电力。 利用激光扫描IC芯片表面，并跟踪IC芯片表面上的激光束照射位置。 激光扫描加热扫描IC芯片表面下方的有源电气元件。 测量IC芯片电接口的频率响应并将其与辐射位置相关联。 响应于识别超过噪声阈值的位置相关频率测量来确定IC芯片缺陷区域。 例如，频率测量可以与模具表面位置相关联，并且如果频率测量超过噪声阈值，则该表面积下面的电路可能被识别为有缺陷的。 通常，管芯缺陷区域在约1赫兹和10千赫兹之间的频率范围内的测量值相关联。

公开(公告)号：US08268669B2

公开(公告)日：2012-09-18

申请号：US13050822

申请日：2011-03-17

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/544 ,  G01R31/2853 ,  G01R31/308 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.

Abstract translation: 提供了一种用于在集成电路（IC）封装中检测激光光路的方法。 该方法提供封装在玻璃球和环氧树脂化合物中的IC封装。 电源供给IC。 IC用激光扫描。 通常，使用由IC封装的环氧化合物中的玻璃球最少吸收的激光波长，并且检测到对IC的电流的变化。 检测到的电流变化与扫描的IC封装表面区域相互参照。 该过程识别扫描的IC封装表面区域下面的光学路径。 在一些方面，该过程导致了在光学路径下面的玻璃球收集包装结构的识别。 玻璃球收集结构的实例可以包括内部引线，引线框架边缘或管芯边缘。

公开(公告)号：US08106665B2

公开(公告)日：2012-01-31

申请号：US12388200

申请日：2009-02-18

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G01R31/311

CPC classification number: G01R31/311

Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.

Abstract translation: 提供了一种用于三维集成电路（IC）故障分析的反射器工具和方法。 IC（模具）具有顶面和底面，周边和第一面。 IC电连接到电流感测放大器。 在IC电流的变化被感测到的同时，用红外激光束在X平面上扫描IC的第一面。 感测的电流变化与X平面中的红外激光束的位置相交。 在一个方面，在X平面中的第一面上以Y平面中相应的多个步骤执行多次扫描，使得电流变化可以与X和Y平面中的位置交叉参考。 通过IC侧的这种2-D分析，人类操作员或软件程序可以确定IC中的缺陷。

公开(公告)号：US20090322343A1

公开(公告)日：2009-12-31

申请号：US12388200

申请日：2009-02-18

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G01R31/00 ,  G02B5/08 ,  G02B3/06

CPC classification number: G01R31/311

Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.

Abstract translation: 提供了一种用于三维集成电路（IC）故障分析的反射器工具和方法。 IC（模具）具有顶面和底面，周边和第一面。 IC电连接到电流感测放大器。 在IC电流的变化被感测到的同时，用红外激光束在X平面上扫描IC的第一面。 感测的电流变化与X平面中的红外激光束的位置相交。 在一个方面，在X平面中的第一面上以Y平面中相应的多个步骤执行多次扫描，使得电流变化可以与X和Y平面中的位置交叉参考。 通过IC侧的这种2-D分析，人类操作员或软件程序可以确定IC中的缺陷。

公开(公告)号：US08106671B2

公开(公告)日：2012-01-31

申请号：US12541058

申请日：2009-08-13

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G01R31/20 ,  G01R1/067 ,  G01R31/26

CPC classification number: G01R1/0408

Abstract: A socketless integrated circuit (IC) contact connector is provided with an electrically conductive support post. An electrically conductive spring has a first end connected to the post, and a second end. An electrically conductive first wire has a first end connected to the spring second end, and a second end. An electrically conductive loop with a loop neck is connected to the first wire second end. Typically, the loop is formed in the first wire second end. The spring and loop work in cooperation to engage an IC contact.

Abstract translation: 无插座集成电路（IC）接触连接器设置有导电支撑柱。 导电弹簧具有连接到柱的第一端和第二端。 导电的第一线具有连接到弹簧第二端的第一端和第二端。 具有环颈的导电环连接到第一线第二端。 通常，环形成在第一线第二端。 春天和环路合作，共同开展IC联络。

公开(公告)号：US07977967B2

公开(公告)日：2011-07-12

申请号：US12830122

申请日：2010-07-02

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: H03K19/00

CPC classification number: H01C7/008

Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.

Abstract translation: 提供了一种用于热电二进制逻辑控制的方法。 该方法接受表示输入逻辑状态的输入电压。 响应于输入电压来控制加热基准。 该方法响应于热参考提供表示输出逻辑状态的输出电压。 更明确地说，热参考控制温度敏感分压器的输出电压。 例如，温度敏感分压器可以是热敏电阻分压器。

公开(公告)号：US20100289488A1

公开(公告)日：2010-11-18

申请号：US12466239

申请日：2009-05-14

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G02F1/09 ,  G01R33/032

CPC classification number: G01R33/0325

Abstract: System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity.

Abstract translation: 提供了用于光磁克尔效应信号分析的系统和方法。 在一个方面，提供具有平行导线的测试夹具，其中第一线的输入与第二线的电阻加载输出相邻，并且与第二线的输入相邻的第一线的电阻加载输出。 导电线之间插有光学透明的测试区域，金属反射体位于测试区域的正下方。 信号参考提供给第一行的输入，被测信号被提供给第二行的输入。 具有第一偏振角的光束通过测试区域聚焦到反射器上。 测量反射光的强度，并且可以响应于测量的光强度来确定被测信号和参考信号之间的相似性。

公开(公告)号：US20100277221A1

公开(公告)日：2010-11-04

申请号：US12830122

申请日：2010-07-02

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: H01L37/00

CPC classification number: H01C7/008

Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.

Abstract translation: 提供了一种用于热电二进制逻辑控制的方法。 该方法接受表示输入逻辑状态的输入电压。 响应于输入电压来控制加热基准。 该方法响应于热参考提供表示输出逻辑状态的输出电压。 更明确地说，热参考控制温度敏感分压器的输出电压。 例如，温度敏感分压器可以是热敏电阻分压器。

公开(公告)号：US20090206883A1

公开(公告)日：2009-08-20

申请号：US12270781

申请日：2008-11-13

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: H03K19/20

CPC classification number: H03K19/02

Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.

Abstract translation: 热电（TE）二进制NAND门逻辑电路提供了一种用于NAND逻辑门控的方法。 该方法接受表示输入二进制逻辑状态的第一输入电压，并且响应于第一输入电压产生第一热电（TE）温度。 接受表示输入二进制逻辑状态的第二输入电压，并且响应于第二输入电压产生第二TE温度。 响应于第一和第二TE温度，产生NAND逻辑状态输出电压。 更明确地，响应于第一TE温度产生第一控制电压，并且响应于第二TE温度产生第二控制电压。 然后，响应于第一和第二控制电压产生第三TE温度，其又产生输出电压。

公开(公告)号：US08394244B1

公开(公告)日：2013-03-12

申请号：US12566600

申请日：2009-09-24

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: C23C14/00 ,  C23C14/32 ,  G01R31/26 ,  H01L21/66 ,  H01L21/00

CPC classification number: H01L21/67086 ,  H01L23/3185 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for laser patterning an integrated circuit (IC) etching mask. The method provides an IC packaged die with a first region underlying a backside surface of a bulk silicon (Si) layer. An etch-resistant film is formed overlying the backside surface. Alternately, the entire IC die package is conformally coated. A semi-transparent film is formed overlying the etch-resistant film, semi-transparent to light having a first wavelength. In response to irradiating the semi-transparent film with light having a first power density, an IC die first region is located. In response to irradiating the semi-transparent film with a laser light having a second power density, greater than the first power density, an area of etch-resistant film overlying the first region is decomposed. More explicitly, an area of semi-transparent film overlying the first region is ablated, and the etch-resistant film underlying the ablated semi-transparent film is heated.

Abstract translation: 提供了一种用于激光图案化集成电路（IC）蚀刻掩模的方法。 该方法提供具有在体硅（Si）层的背侧表面下方的第一区域的IC封装的管芯。 形成覆盖在背面上的耐蚀刻膜。 或者，整个IC管芯封装被保形涂覆。 形成半透明膜，覆盖耐蚀刻膜，半透明至具有第一波长的光。 响应于用具有第一功率密度的光照射半透明膜，定位IC芯片第一区域。 响应于用具有大于第一功率密度的第二功率密度的激光照射半透明膜，分解覆盖在第一区域上的耐蚀刻膜的面积。 更明确地说，覆盖在第一区域上的半透明膜的区域被烧蚀，并且被烧蚀的半透明膜下面的耐蚀刻膜被加热。