公开(公告)号：US09921592B2

公开(公告)日：2018-03-20

申请号：US14129525

申请日：2013-09-09

申请人： Joseph Shor ,  George L. Geannopoulos ,  Fabrice Paillet ,  Lan D. Vu ,  Oleg Dadashev

发明人： Joseph Shor ,  George L. Geannopoulos ,  Fabrice Paillet ,  Lan D. Vu ,  Oleg Dadashev

IPC分类号： G05F3/30 ,  G05F1/46 ,  G05F1/575 ,  G05F1/59 ,  G06F1/26

CPC分类号： G05F1/468 ,  G05F1/575 ,  G05F1/59 ,  G05F3/30 ,  G06F1/26

摘要： Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.

公开(公告)号：US20050232024A1

公开(公告)日：2005-10-20

申请号：US10826375

申请日：2004-04-19

申请人： Shahar Atir ,  Oleg Dadashev ,  Yair Sofer ,  Eduardo Maayan

发明人： Shahar Atir ,  Oleg Dadashev ,  Yair Sofer ,  Eduardo Maayan

IPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/26

摘要： There is provided in accordance with embodiments of the present invention a method of reducing the neighbor effect in reading data in a non-volatile memory array by sensing adjacent memory cells in a virtual ground array of memory cells comprising sensing substantially simultaneously a state of adjacent memory cells, wherein a bit stored in a charge trapping region of each cell of the adjacent memory cells is in an identical state.

摘要翻译： 根据本发明的实施例提供了一种通过感测存储器单元的虚拟接地阵列中的相邻存储器单元来减少在非易失性存储器阵列中读取数据中的相邻效应的方法，包括基本同时感测相邻存储器的状态 单元，其中存储在相邻存储器单元的每个单元的电荷捕获区域中的位处于相同状态。

公开(公告)号：US06836443B2

公开(公告)日：2004-12-28

申请号：US10341933

申请日：2003-01-14

申请人： Oleg Dadashev

发明人： Oleg Dadashev

IPC分类号： G11C702

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C2207/063 ,  G11C2207/2227

摘要： A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.

摘要翻译： 用于存储器阵列中的存储单元的感测系统包括电流积分器电路，其被配置为将通过存储器单元的读取电流与通过参考存储单元的参考电流进行积分。 积分过程创建一组可用于确定存储单元状态的差分测量电压。 通过集成读取电流以获得测量电压，而不是直接将读取电流与参考电流进行比较，感测系统可以使用比常规感测系统更低的电源电压。 此外，由于通过对随时间的读取电流进行积分而产生测量电压，因此感测操作对电源电压波动和精度较不敏感。 此外，对于显示小读取电流的存储单元，可以通过增加积分周期来增加感测操作的精度。

公开(公告)号：US20120063238A1

公开(公告)日：2012-03-15

申请号：US13301826

申请日：2011-11-22

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

公开(公告)号：US07532529B2

公开(公告)日：2009-05-12

申请号：US11464253

申请日：2006-08-14

申请人： Oleg Dadashev ,  Yoram Betser ,  Eduardo Maayan

发明人： Oleg Dadashev ,  Yoram Betser ,  Eduardo Maayan

IPC分类号： G11C7/02

CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

摘要： A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.

摘要翻译： 一种用于感测从存储器阵列内的阵列单元接收的信号的方法，所述方法包括以下步骤：产生与所述存储器阵列的所选阵列单元的电流成比例的模拟电压Vddr，以及将所述模拟电压Vddr与参考 模拟电压Vcomp以产生输出数字信号。 还提供了一种用于通过将来自存储器单元的信号变换为时间延迟来感测存储单元的方法，以及通过将时间延迟与参考单元的时间延迟进行比较来感测存储单元。 还公开了相关装置。

公开(公告)号：US06469929B1

公开(公告)日：2002-10-22

申请号：US09935013

申请日：2001-08-21

申请人： Alexander Kushnarenko ,  Oleg Dadashev

发明人： Alexander Kushnarenko ,  Oleg Dadashev

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C7/062 ,  G11C7/12 ,  G11C16/24

摘要： A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. Thus, sensing the state of the memory cell is substantially independent of the size of the memory array. A sensing system for sensing the state of a memory cell can include a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a static clamp to charge the system bit line to a first predetermined voltage and a dynamic clamp to charge the system bit line to a second predetermined voltage.

摘要翻译： 用于感测存储器单元的状态的方法包括耦合到存储器单元的位线的动态和静态钳位。 这种双钳位配置/操作确保了位线的快速充电，同时消除了位线的过充电。 因此，感测存储器单元的状态基本上与存储器阵列的大小无关。 用于感测存储器单元的状态的感测系统可以包括耦合到存储器单元的端子的系统位线，用于激活系统位线上的充电操作的充电启动装置，以及连接在系统位之间的控制单元 线和充电引发装置。 控制单元包括用于将系统位线充电到第一预定电压的静态钳位电路和用于将系统位线充电到第二预定电压的动态钳位电路。

公开(公告)号：US06456557B1

公开(公告)日：2002-09-24

申请号：US09941451

申请日：2001-08-28

申请人： Oleg Dadashev ,  Kyra Jacob

发明人： Oleg Dadashev ,  Kyra Jacob

IPC分类号： G11C700

CPC分类号： G11C7/227 ,  G11C5/147 ,  G11C7/1006 ,  G11C7/1048 ,  G11C8/08 ,  G11C16/0491 ,  G11C16/30

摘要： A memory device includes a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells by including in its feedback path an emulated multiplexing circuit having an identical resistance to that of the multiplexing circuit. The voltage regulator also includes a differential amplifier, a pull-up transistor for generating a reference voltage, and a first clamp transistor controlled by the reference voltage to pass a desired voltage level to the multiplexing circuit. The feedback path incorporates the emulator circuit between a second clamp transistor and a voltage divider. Because the emulation and multiplexing circuits have the same resistance, the voltage passed to the voltage divider is essentially identical to the voltage passed by the multiplexing circuit to a selected memory cell, thereby allowing the voltage regulator to produce an optimal voltage level at the selected memory cell.

摘要翻译： 存储器件包括电压调节器，其通过在其反馈路径中包括具有与复用电路的电阻相同的电阻的仿真复用电路来补偿用于访问存储器单元的位线控制（复用）电路中的电阻变化。 电压调节器还包括差分放大器，用于产生参考电压的上拉晶体管和由参考电压控制的第一钳位晶体管，以将所需的电压电平传递到多路复用电路。 反馈路径包含在第二钳位晶体管和分压器之间的仿真器电路。 由于仿真和多路复用电路具有相同的电阻，所以传递到分压器的电压基本上与多路复用电路经过选定存储单元的电压相同，从而允许电压调节器在所选存储器处产生最佳电压电平 细胞。

公开(公告)号：US20090073774A1

公开(公告)日：2009-03-19

申请号：US12232437

申请日：2008-09-17

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 可以根据每个地址的预定义表来选择预充电的全局位线。 可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。

公开(公告)号：US07202654B1

公开(公告)日：2007-04-10

申请号：US11236359

申请日：2005-09-27

申请人： Oleg Dadashev ,  Alexander Kushnarenko

发明人： Oleg Dadashev ,  Alexander Kushnarenko

IPC分类号： G05F3/16

CPC分类号： G05F3/262

摘要： A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . . Tn, wherein the transistor T1 is connected to a node n0, to which is connected another transistor T0 that receives an input bias voltage Vbias, and wherein a feedback voltage fb from node n0 is fed to an input of the differential amplifier, the differential amplifier receiving an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd, the differential amplifier outputting to an NMOS transistor M, and wherein the high voltage regulator has a large diode stack gain and lower GDA*GNMOS*m, resulting in a generally constant feedback (loop) gain Gloop, wherein the loop gain is given by: Loop Gain=Gloop=Gstack*GDA*GNMOS*m wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1, Gstack is the gain of the diode stack, GDA is the gain of the differential amplifier and GNMOS is the gain of the NMOS transistor M.

摘要翻译： 一种高电压调节器，包括包括一对晶体管的电流镜，其中一个晶体管连接到输出输出电压V OUT的节点;二极管叠层，包括多个串联连接的晶体管T T 1，T 2，...，N 2， 。 。 其中晶体管T 1连接到与另一个晶体管T 0连接的节点n 0 0 < SUB>接收输入偏置电压V SUB偏置，并且其中来自节点n0的反馈电压fb​​被馈送到差分放大器的输入端，差分放大器接收 输入参考电压V SUB参考电压，并且还连接到正电压源Vdd，该差分放大器输出到NMOS晶体管M，并且其中高压调节器具有大的二极管叠层 增益和更低的G N N N * N，导致大体上恒定的反馈（环路）增益G ，其中环路增益为 给了

公开(公告)号：US20070069711A1

公开(公告)日：2007-03-29

申请号：US11236359

申请日：2005-09-27

申请人： Oleg Dadashev ,  Alexander Kushnarenko

发明人： Oleg Dadashev ,  Alexander Kushnarenko

IPC分类号： G05F3/16

CPC分类号： G05F3/262

摘要： A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . . Tn, wherein the transistor T1 is connected to a node n0, to which is connected another transistor T0 that receives an input bias voltage Vbias, and wherein a feedback voltage fb from node n0 is fed to an input of the differential amplifier, the differential amplifier receiving an input reference voltage Vref at one of its other inputs, and is also connected to positive voltage supply Vdd, the differential amplifier outputting to an NMOS transistor M, and wherein the high voltage regulator has a large diode stack gain and lower GDA*GNMOS*m, resulting in a generally constant feedback (loop) gain Gloop wherein the loop gain is given by: Loop Gain=Gloop=Gstack*GDA*GNMOS*m wherein m is the ratio of the two currents I1 and I2, that is, I2=mI1, Gstack is the gain of the diode stack, GDA is the gain of the differential amplifier and GNMOS is the gain of the NMOS transistor M.

摘要翻译： 一种高电压调节器，包括包括一对晶体管的电流镜，其中一个晶体管连接到输出输出电压V OUT的节点;二极管叠层，包括多个串联连接的晶体管T T 1，T 2，...，N 2， 。 。 其中晶体管T 1连接到与另一个晶体管T 0连接的节点n 0 0 < SUB>接收输入偏置电压V SUB偏置，并且其中来自节点n0的反馈电压fb​​被馈送到差分放大器的输入端，差分放大器接收 输入参考电压V SUB参考电压，并且还连接到正电压源Vdd，该差分放大器输出到NMOS晶体管M，并且其中高压调节器具有大的二极管叠层 增益和较低的G N N N N N * M，导致通常恒定的反馈（环路）增益G 其中给出了环路增益 通过：<？in-line-formula description =“In-line Formulas”end =“lead”？> Loop Gain = G = G 其中m是两个电流I的比值，其中m是两个电流I的比值 ＆lt; 1＆gt;和＆lt; 2＆gt;，即I 2＆gt; = m 1＆lt; 1＆lt;＆lt; >是二极管堆叠的增益，G 是差分放大器的增益，并且G NMOS NMOS是NMOS晶体管M的增益。