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181 条记录 (耗时 0.049 秒)

    Fin Fet device with independent control gate
    4.
    发明授权
    Fin Fet device with independent control gate 有权
    Fin Fet设备具有独立的控制门

    公开(公告)号：US09214529B2

    公开(公告)日：2015-12-15

    申请号：US13047132

    申请日：2011-03-14

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-hsun Lin

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-hsun Lin

    IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  B82Y10/00

    CPC分类号： H01L29/66545 ,  B82Y10/00 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

    摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.

    摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。

    Collapsable gate for deposited nanostructures
    5.
    发明授权
    Collapsable gate for deposited nanostructures 失效
    用于沉积的纳米结构的可折叠门

    公开(公告)号：US08492748B2

    公开(公告)日：2013-07-23

    申请号：US13169542

    申请日：2011-06-27

    申请人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

    发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

    IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L51/40

    CPC分类号： H01L29/66045 ,  H01L51/055

    摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

    摘要翻译： 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

    High selectivity nitride etch process
    9.
    发明授权
    High selectivity nitride etch process 有权
    高选择性氮化物蚀刻工艺

    公开(公告)号：US08765613B2

    公开(公告)日：2014-07-01

    申请号：US13281688

    申请日：2011-10-26

    申请人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Michael A. Guillorn ,  Masahiro Nakamura

    发明人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Michael A. Guillorn ,  Masahiro Nakamura

    IPC分类号： H01L21/302

    CPC分类号： H01L29/6653 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/6659

    摘要： An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.

    摘要翻译： 各向异性氮化硅蚀刻通过在硅表面和氧化硅表面上形成含氟代烃的聚合物来提供对硅和氧化硅的选择性。 使用选择性氟代烃沉积来提供对非氮化物表面的选择性。 含氟烃聚合物与氮化硅相互作用以形成挥发性化合物，从而能够蚀刻氮化硅。 含氟烃聚合物以低反应速率与氧化硅相互作用，阻止或完全停止氧化硅的蚀刻。 含氟烃聚合物不与硅相互作用，并保护硅免受等离子体的影响。 可以采用各向异性氮化硅蚀刻来蚀刻任选尺寸的硅和氧化硅的氮化硅，包括小于50nm的小尺寸。

    Gap-fill keyhole repair using printable dielectric material
    10.
    发明授权
    Gap-fill keyhole repair using printable dielectric material 失效

    公开(公告)号：US08703576B2

    公开(公告)日：2014-04-22

    申请号：US13232293

    申请日：2011-09-14

    申请人： Paul Chang ,  Josephine B. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    发明人： Paul Chang ,  Josephine B. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    IPC分类号： H01L21/76

    CPC分类号： H01L29/51 ,  H01L21/311 ,  H01L21/76825 ,  H01L21/76837 ,  H01L29/66545

    摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.