利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.032 秒)

    HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    2.
    发明申请
    HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    高K介电金属栅组件结构及其形成方法

    公开(公告)号：US20090108365A1

    公开(公告)日：2009-04-30

    申请号：US11926830

    申请日：2007-10-29

    申请人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    发明人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    IPC分类号： H01L27/092 ,  H01L21/3205

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.

    摘要翻译： 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。 用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂 具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

    High-K dielectric metal gate device structure
    3.
    发明申请
    High-K dielectric metal gate device structure 有权
    高K电介质金属栅极器件结构

    公开(公告)号：US20100044800A1

    公开(公告)日：2010-02-25

    申请号：US12589421

    申请日：2009-10-23

    申请人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    发明人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric.

    摘要翻译： 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。

    High-k dielectric metal gate device structure and method for forming the same
    4.
    发明授权
    High-k dielectric metal gate device structure and method for forming the same 有权
    高k电介质金属栅极器件结构及其形成方法

    公开(公告)号：US07625791B2

    公开(公告)日：2009-12-01

    申请号：US11926830

    申请日：2007-10-29

    申请人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    发明人： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.

    摘要翻译： 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。 用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂 具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

    CMOS dual metal gate semiconductor device
    5.
    发明授权
    CMOS dual metal gate semiconductor device 有权
    CMOS双金属栅极半导体器件

    公开(公告)号：US08836038B2

    公开(公告)日：2014-09-16

    申请号：US12883241

    申请日：2010-09-16

    申请人： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

    发明人： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66

    CPC分类号： H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

    摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

    摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING
    8.
    发明申请
    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING 审中-公开
    新型高K金属结构及其制备方法

    公开(公告)号：US20100044804A1

    公开(公告)日：2010-02-25

    申请号：US12427222

    申请日：2009-04-21

    申请人： Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    发明人： Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

    摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底，形成在衬底中的晶体管，晶体管包括形成在衬底上的高k栅极电介质，高k栅极电介质具有从一个侧壁到 高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极，金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度，第二长度小于 第一长。