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    Field-effect transistor with local source/drain insulation and associated method of production
    1.
    发明授权
    Field-effect transistor with local source/drain insulation and associated method of production 有权
    具有局部源/漏绝缘和相关生产方法的场效应晶体管

    公开(公告)号：US07824993B2

    公开(公告)日：2010-11-02

    申请号：US12431214

    申请日：2009-04-28

    申请人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

    发明人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

    摘要： A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

    摘要翻译： 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。 此外，在半导体衬底中的栅极堆叠处形成源极和漏极凹陷的步骤包括形成用于实现半导体衬底中的沟道连接区域的第一凹陷，在栅极堆叠处形成间隔物，并且使用间隔件形成第二凹陷 作为第一凹部和半导体衬底中的掩模。

    Field-effect transistor with local source/drain insulation and associated method of production
    2.
    发明授权
    Field-effect transistor with local source/drain insulation and associated method of production 有权
    具有局部源/漏绝缘和相关生产方法的场效应晶体管

    公开(公告)号：US09240462B2

    公开(公告)日：2016-01-19

    申请号：US12888938

    申请日：2010-09-23

    申请人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

    发明人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

    摘要： A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

    摘要翻译： 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。

    VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH
    5.
    发明申请
    VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH 有权
    通过选择性外延生长形成硅的垂直二极管

    公开(公告)号：US20090085163A1

    公开(公告)日：2009-04-02

    申请号：US11862964

    申请日：2007-09-27

    申请人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

    发明人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

    IPC分类号： H01L29/861 ,  H01L21/329

    CPC分类号： H01L29/861 ,  H01L29/6609 ,  H01L29/66356 ,  H01L29/7391

    摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

    摘要翻译： 一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。 一些实施例包括引起垂直和横向二极管活动的装置。 一些实施例包括用于翅片半导体装置的门控垂直二极管。 工艺实施例包括形成垂直二极管装置。

    Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement
    6.
    发明申请
    Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement 审中-公开
    多翅片组件布置和制造多鳍组件布置的方法

    公开(公告)号：US20080283925A1

    公开(公告)日：2008-11-20

    申请号：US12124369

    申请日：2008-05-21

    申请人： Joerg Berthold ,  Christian Pacha ,  Klaus Schruefer ,  Klaus Von Arnim

    发明人： Joerg Berthold ,  Christian Pacha ,  Klaus Schruefer ,  Klaus Von Arnim

    IPC分类号： H01L27/088 ,  H01L21/82

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/785

    摘要： In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another.

    摘要翻译： 在第一实施例中，多翅片部件布置具有多个多翅片部件部分布置。 多片组件部分布置中的每一个具有多个电子部件，该电子部件具有多鳍结构。 至少一个多翅片部件部分布置具有至少一个虚拟结构，在形成于至少一个多翅片部件部分布置中的至少两个电子部件之间形成至少一个虚拟结构。 虚拟结构形成为使得形成在多翅片部件部分布置中的电子部件的电特性彼此适配。

    Vertical diode using silicon formed by selective epitaxial growth
    8.
    发明授权
    Vertical diode using silicon formed by selective epitaxial growth 有权
    使用通过选择性外延生长形成的硅的垂直二极管

    公开(公告)号：US08318553B2

    公开(公告)日：2012-11-27

    申请号：US12986875

    申请日：2011-01-07

    申请人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

    发明人： Christian Russ ,  Christian Pacha ,  Snezana Jenei ,  Klaus Schruefer

    IPC分类号： H01L21/36 ,  H01L21/329

    CPC分类号： H01L29/861 ,  H01L29/6609 ,  H01L29/66356 ,  H01L29/7391

    摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

    摘要翻译： 一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。 一些实施例包括引起垂直和横向二极管活动的装置。 一些实施例包括用于翅片半导体装置的门控垂直二极管。 工艺实施例包括形成垂直二极管装置。

    FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE
    9.
    发明申请
    FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE 有权
    具有结构的场效应晶体管

    公开(公告)号：US20110031530A1

    公开(公告)日：2011-02-10

    申请号：US12860075

    申请日：2010-08-20

    申请人： Klaus Schruefer

    发明人： Klaus Schruefer

    IPC分类号： H01L29/737

    CPC分类号： H01L29/802 ,  H01L29/78684 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/936

    摘要： A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

    摘要翻译： 具有异质结构的场效应晶体管包括形成在载体材料上的应变单晶半导体层，其具有由作为最上层的第一半导体材料（Si）制成的弛豫单晶半导体层。 应变单晶半导体层具有可以自由地设定第二半导体材料的比例x的半导体合金（GexSi1-x）。 此外，在应变半导体层上形成栅极绝缘层和栅极层。 为了限定未掺杂的沟道区，至少在应变半导体层中，相对于栅极层横向形成漏极/源极区。 自由设定Ge比例x的可能性使得能够根据需要设定阈值电压，由此可以实现现代逻辑半导体部件。

    Field effect transistor with a heterostructure and associated production method
    10.
    发明申请
    Field effect transistor with a heterostructure and associated production method 有权
    具有异质结构和相关生产方法的场效应晶体管

    公开(公告)号：US20070013002A1

    公开(公告)日：2007-01-18

    申请号：US11473430

    申请日：2006-06-23

    申请人： Klaus Schruefer

    发明人： Klaus Schruefer

    IPC分类号： H01L27/12

    CPC分类号： H01L29/802 ,  H01L29/78684 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/936

    摘要： A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

    摘要翻译： 具有异质结构的场效应晶体管包括形成在载体材料上的应变单晶半导体层，其具有由作为最上层的第一半导体材料（Si）制成的弛豫单晶半导体层。 应变单晶半导体层具有可以自由地设定第二半导体材料的比例x的半导体合金（GexSi1-x）。 此外，在应变半导体层上形成栅极绝缘层和栅极层。 为了限定未掺杂的沟道区，至少在应变半导体层中，相对于栅极层横向形成漏极/源极区。 自由设定Ge比例x的可能性使得能够根据需要设定阈值电压，由此可以实现现代逻辑半导体部件。