公开(公告)号：US07012452B2

公开(公告)日：2006-03-14

申请号：US10920114

申请日：2004-08-17

申请人： Jun Honda ,  Jong-Deog Jeong

发明人： Jun Honda ,  Jong-Deog Jeong

IPC分类号： H03B1/00

CPC分类号： H03F3/21

摘要： An integrated high-voltage linear amplifier IC with reduced power dissipation, faster operation, and small die size, comprising a low side well and a floating high side well; an error amplifier for receiving a noise signal; a level shifting circuit in the low side well for outputting a current mode error signal based on the noise signal to the high side well in differential current mode for noise reduction; and a drive circuit in the high side well. A voltage/current converter receives a voltage mode error signal based on the noise signal and supplies the current input signal. Current mirror circuitry and the drive circuit in the high side well outputs a sum current derived from the current mode error signal for driving external power devices.

摘要翻译： 集成的高压线性放大器IC，功耗降低，运行更快，管芯尺寸小，包括一个低侧井和一个浮动的高侧井; 用于接收噪声信号的误差放大器; 在低侧阱中的电平移动电路，用于在用于降噪的差分电流模式中将基于噪声信号的电流模式误差信号输出到高侧阱; 和高压侧的驱动电路。 电压/电流转换器基于噪声信号接收电压模式误差信号并提供电流输入信号。 电流镜电路和高侧阱中的驱动电路输出由电流模式误差信号导出的和电流，用于驱动外部功率器件。

公开(公告)号：US08638088B2

公开(公告)日：2014-01-28

申请号：US13019490

申请日：2011-02-02

申请人： Jun Honda ,  Jong-Deog Jeong

发明人： Jun Honda ,  Jong-Deog Jeong

IPC分类号： G01R25/00

CPC分类号： H03F3/217 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

摘要： In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

摘要翻译： 在一个实施例中，提供了用于检测开关模式功率转换器中的负载的方法。 开关式功率转换器包括被分别由高侧和低侧驱动信号驱动以提供开关电压的高侧和低侧功率开关。 高低侧驱动信号包括多个死区时间。 该方法包括监视开关电压的波形和高侧和低侧驱动信号中的至少一个。 将开关电压的监视波形与高侧和低侧驱动信号中的至少一个驱动信号的监视波形进行比较，以在至少一个死区时间段内确定开关电压是高电平还是低电平。 基于在至少一个死区时间段期间开关电压是高还是低来确定负载的当前测量。

公开(公告)号：US20070139109A1

公开(公告)日：2007-06-21

申请号：US11612933

申请日：2006-12-19

申请人： Jun Honda ,  Jong-Deog Jeong

发明人： Jun Honda ,  Jong-Deog Jeong

IPC分类号： H03F3/217

CPC分类号： H03F1/305 ,  H03F3/2171 ,  H03F2200/03 ,  H03F2200/78

摘要： A circuit for minimizing audible click noise upon the startup of a Class D audio power amplifier. The amplifier including a power switching output stage and a driver for driving the output stage receiving a driving signal and a shutdown signal, the shutdown signal preventing switching of the output stage. The circuit including a comparator connected to the driver for generating the driving signal; an error amplifier receiving an audio input signal; a first feedback loop for connecting the output stage as input to an input of the error amplifier, an output of the error amplifier being connected to an output of the comparator; and a circuit coupled to the error amplifier preventing a capacitor connected to the error amplifier from excessively charging, thereby preventing noise in the output stage when the shutdown signal is removed.

摘要翻译： 一种用于在D类音频功率放大器启动时最小化噪音的电路。 放大器包括功率开关输出级和用于驱动输出级接收驱动信号和关断信号的驱动器，该关断信号防止输出级的切换。 该电路包括连接到驱动器的比较器，用于产生驱动信号; 接收音频输入信号的误差放大器; 用于将输出级作为输入连接到误差放大器的输入的第一反馈回路，误差放大器的输出端连接到比较器的输出; 以及耦合到误差放大器的电路，防止连接到误差放大器的电容器过度充电，从而防止在关闭信号被去除时在输出级中的噪声。

公开(公告)号：US20120194170A1

公开(公告)日：2012-08-02

申请号：US13019490

申请日：2011-02-02

申请人： Jun Honda ,  Jong-Deog Jeong

发明人： Jun Honda ,  Jong-Deog Jeong

IPC分类号： G01R25/00

CPC分类号： H03F3/217 ,  H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

摘要： In one embodiment, a method for detecting a load in a switched-mode power converter is provided. The switched-mode power converter includes high and low-side power switches which are configured to be driven respectively by high and low-side drive signals to provide a switching voltage. The high and low-side drive signals include a plurality of dead-time periods. The method includes monitoring a waveform of the switching voltage and at least one of the high and low-side drive signals. The monitored waveform of the switching voltage is compared to the monitored waveform of the at least one of the high and low-side drive signals to determine whether the switching voltage is high or low during at least one of the dead-time periods. A current measurement of the load is determined based on whether the switching voltage is high or low during the at least one of the dead-time periods.

摘要翻译： 在一个实施例中，提供了用于检测开关模式功率转换器中的负载的方法。 开关式功率转换器包括被分别由高侧和低侧驱动信号驱动以提供开关电压的高侧和低侧功率开关。 高低侧驱动信号包括多个死区时间。 该方法包括监视开关电压的波形和高侧和低侧驱动信号中的至少一个。 将开关电压的监视波形与高侧和低侧驱动信号中的至少一个驱动信号的监视波形进行比较，以在至少一个死区时间段内确定开关电压是高电平还是低电平。 基于在至少一个死区时间段期间开关电压是高还是低来确定负载的当前测量。

公开(公告)号：US20050077928A1

公开(公告)日：2005-04-14

申请号：US10920114

申请日：2004-08-17

申请人： Jun Honda ,  Jong-Deog Jeong

发明人： Jun Honda ,  Jong-Deog Jeong

IPC分类号： G03B1/00 ,  H03B1/00 ,  H03F20060101

CPC分类号： H03F3/21

摘要： An integrated high-voltage linear amplifier IC with reduced power dissipation, faster operation, and small die size, comprising a low side well and a floating high side well; an error amplifier for receiving a noise signal; a level shifting circuit in the low side well for outputting a current mode error signal based on the noise signal to the high side well in differential current mode for noise reduction; and a drive circuit in the high side well. A voltage/current converter receives a voltage mode error signal based on the noise signal and supplies the current input signal. Current mirror circuitry and the drive circuit in the high side well outputs a sum current derived from the current mode error signal for driving external power devices.

摘要翻译： 集成的高压线性放大器IC，功耗降低，运行更快，管芯尺寸小，包括一个低侧井和一个浮动的高侧井; 用于接收噪声信号的误差放大器; 在低侧阱中的电平移动电路，用于在用于降噪的差分电流模式中将基于噪声信号的电流模式误差信号输出到高侧阱; 和高压侧的驱动电路。 电压/电流转换器基于噪声信号接收电压模式误差信号并提供电流输入信号。 电流镜电路和高侧阱中的驱动电路输出由电流模式误差信号导出的和电流，用于驱动外部功率器件。

公开(公告)号：US20050258495A1

公开(公告)日：2005-11-24

申请号：US11130370

申请日：2005-05-16

申请人： Jong-Deog Jeong

发明人： Jong-Deog Jeong

IPC分类号： H01L21/761 ,  H01L27/092 ,  H01L31/113 ,  H03K19/003

CPC分类号： H03K19/00315 ,  H01L21/761 ,  H01L27/092

摘要： A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

摘要翻译： 一种简单，低成本的栅极驱动器和偏置电路提供了超过诸如NMOS和PMOS晶体管的组件的正常分量击穿电压的更宽的工作电压范围。 在该示例中，使用具有外延层作为体积和p型衬底的CMOS工艺来实现电路。

公开(公告)号：US07292088B2

公开(公告)日：2007-11-06

申请号：US11130370

申请日：2005-05-16

申请人： Jong-Deog Jeong

发明人： Jong-Deog Jeong

IPC分类号： H03K17/687

CPC分类号： H03K19/00315 ,  H01L21/761 ,  H01L27/092

摘要： A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

摘要翻译： 一种简单，低成本的栅极驱动器和偏置电路提供了超过诸如NMOS和PMOS晶体管的组件的正常分量击穿电压的更宽的工作电压范围。 在该示例中，使用具有外延层作为体积和p型衬底的CMOS工艺来实现电路。

公开(公告)号：US07336119B2

公开(公告)日：2008-02-26

申请号：US11760440

申请日：2007-06-08

申请人： Jong-Deog Jeong

发明人： Jong-Deog Jeong

IPC分类号： H03K17/687 ,  H01L29/76

CPC分类号： H03K19/00315 ,  H01L21/761 ,  H01L27/092

摘要： A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

摘要翻译： 一种简单，低成本的栅极驱动器和偏置电路提供了超过诸如NMOS和PMOS晶体管的组件的正常分量击穿电压的更宽的工作电压范围。 在该示例中，使用具有外延层作为体积和p型衬底的CMOS工艺来实现电路。

公开(公告)号：US20070229142A1

公开(公告)日：2007-10-04

申请号：US11760440

申请日：2007-06-08

申请人： Jong-Deog Jeong

发明人： Jong-Deog Jeong

IPC分类号： H03K17/687

CPC分类号： H03K19/00315 ,  H01L21/761 ,  H01L27/092

摘要： A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

摘要翻译： 一种简单，低成本的栅极驱动器和偏置电路提供了超过诸如NMOS和PMOS晶体管的组件的正常分量击穿电压的更宽的工作电压范围。 在该示例中，使用具有外延层作为体积和p型衬底的CMOS工艺来实现电路。