Method fabricating semiconductor device using multiple polishing processes
    1.
    发明授权
    Method fabricating semiconductor device using multiple polishing processes 有权
    使用多次抛光工艺制造半导体器件的方法

    公开(公告)号:US08168535B2

    公开(公告)日:2012-05-01

    申请号:US13084657

    申请日:2011-04-12

    IPC分类号: H01L21/44

    摘要: A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.

    摘要翻译: 制造相变存储器件的方法包括使用第一,第二和第三抛光工艺。 第一抛光工艺使用第一牺牲层形成第一接触部分,并且第二抛光工艺使用第二牺牲层形成相变材料图案。 在去除第一和第二牺牲层以暴露第一接触部分的相应突出结构和相变材料图案之后,使用第三抛光工艺来使用绝缘层作为抛光停止层来抛光所得的突出结构。

    NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件,具有该存储器件的存储器件,以及驱动非易失性存储器件的方法

    公开(公告)号:US20110080775A1

    公开(公告)日:2011-04-07

    申请号:US12893413

    申请日:2010-09-29

    IPC分类号: G11C11/00 G11C7/04

    摘要: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

    摘要翻译: 非易失性存储器件包括存储单元阵列,其包括多个非易失性存储单元,每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻,温度补偿电路包括一个或多个参考单元,每个参考单元具有对应于一个 或更多的第二电阻分布,以及包括补偿单元和读出放大器的数据读取电路,所述补偿单元适于向感测节点提供补偿电流,所述补偿电流的量基于每个参考单元的电阻而变化, 并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

    Method of forming a phase changeable structure
    5.
    发明授权
    Method of forming a phase changeable structure 有权
    形成相变结构的方法

    公开(公告)号:US07582568B2

    公开(公告)日:2009-09-01

    申请号:US11625142

    申请日:2007-01-19

    IPC分类号: H01L21/302

    摘要: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern.

    摘要翻译: 本发明涉及形成可变相结构的方法,其中上电极形成在相变层上。 可以向相变层和上电极提供包含氟的材料。 相变层可被蚀刻以形成相变图案。 然后可以将氧等离子体或水蒸气等离子体提供给上电极和相变图案。

    METHODS OF FABRICATING MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES
    6.
    发明申请
    METHODS OF FABRICATING MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES 有权
    制造多层相变记忆体装置的方法

    公开(公告)号:US20090004773A1

    公开(公告)日:2009-01-01

    申请号:US12189477

    申请日:2008-08-11

    IPC分类号: H01L45/00

    摘要: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

    摘要翻译: 可变相存储器件包括相变材料图案,以及电连接到相变材料图案的第一和第二电极。 第一和第二电极被配置为向相变材料图案提供电信号。 相变材料图案包括第一相变材料层和第二相变材料层。 第一和第二可相变材料图案具有不同的化学,物理和/或电特性。 例如,第二相变材料层可以具有比第一相变材料层更大的电阻率。 例如,第一相变材料层可以包括第一浓度的氮,第二相变材料层可以包括大于第一浓度的第二浓度的氮。 还讨论了相关设备和制造方法。

    Magnetic random access memory device and method of forming the same
    8.
    发明申请
    Magnetic random access memory device and method of forming the same 有权
    磁性随机存取存储器件及其形成方法

    公开(公告)号:US20060174473A1

    公开(公告)日:2006-08-10

    申请号:US11347280

    申请日:2006-02-06

    IPC分类号: G11B5/33 G11B5/127 H04R31/00

    摘要: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    摘要翻译: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线,覆盖数字线的中间绝缘层,设置在中间绝缘层上方和数字线上的磁性隧道结(MTJ)图案,MTJ图案包括顺序堆叠 下磁性图案,上磁性图案和封盖图案,其中封盖图案在高于约280℃的温度下不与上磁性图案反应,而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线,形成覆盖数字线的中间绝缘层,在中间绝缘层上形成磁隧道结(MTJ)图案,MTJ图案包括顺序层叠的 较低的磁性图案,上部磁性图案和封盖图案,其中封盖图案在高于约280℃的温度下不与上部磁性图案反应,在约350℃或更高的温度下进行退火操作, 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。