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    Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods
    1.
    发明申请
    Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods 审中-公开
    沟槽隔离方法，使用沟槽隔离方法形成栅极结构的方法和使用沟槽隔离方法制造非易失性存储器件的方法

    公开(公告)号：US20080044981A1

    公开(公告)日：2008-02-21

    申请号：US11769042

    申请日：2007-06-27

    申请人： Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

    发明人： Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

    IPC分类号： H01L21/3205 ,  H01L21/762

    CPC分类号： H01L21/76232

    摘要： Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask. The trench is substantially narrower than the second opening and has a sidewall that has a second inclination angle that is substantially larger than the first inclination angle.

    摘要翻译： 提供制造包括在半导体衬底上形成掩模图案的半导体器件的方法。 掩模图案限定了至少部分地暴露半导体衬底并且在衬垫氧化物层图案上包括衬垫氧化物层和氮化物层图案的第一开口。 氮化物层具有基本上大于衬垫氧化物层图案的线宽。 通过至少部分去除通过第一开口暴露的半导体衬底的一部分，形成连接到第一开口的第二开口。 第二开口具有具有第一倾斜角并且至少部分地暴露半导体衬底的侧壁。 通过使用掩模图案蚀刻通过第二开口暴露的半导体衬底的一部分来形成连接到第二开口的沟槽作为蚀刻掩模。 沟槽基本上比第二开口窄，并且具有侧壁，该侧壁的第二倾斜角度基本上大于第一倾斜角度。

    Method of manufacturing a memory device
    2.
    发明申请
    Method of manufacturing a memory device 审中-公开
    制造存储器件的方法

    公开(公告)号：US20080014729A1

    公开(公告)日：2008-01-17

    申请号：US11820516

    申请日：2007-06-20

    申请人： Woong Lee ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park ,  Ho-Min Son ,  Won-Jun Jang

    发明人： Woong Lee ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park ,  Ho-Min Son ,  Won-Jun Jang

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/40114

    摘要： In a method of manufacturing a memory device, a tunnel insulation layer and a floating gate layer are formed on a semiconductor substrate. A top surface of the floating gate layer is converted into a first nitride layer by a first nitridation treatment process. The first nitride layer is converted into a first oxynitride layer by a radical oxidation process. A lower oxide layer is formed on the first oxynitride layer by an LPCVD process. A second nitride layer and an upper oxide layer are formed on the lower oxide layer. A conductive layer is formed on the upper oxide layer. Thus, a multi-layered dielectric layer including the first oxynitride layer, the lower oxide layer, the second nitride layer, the upper oxide layer and the densified second oxynitride layer may have an increased capacitance without having degenerated leakage current characteristics.

    摘要翻译： 在制造存储器件的方法中，在半导体衬底上形成隧道绝缘层和浮栅层。 通过第一氮化处理工艺将浮栅层的顶表面转化为第一氮化物层。 第一氮化物层通过自由基氧化法转化为第一氮氧化物层。 通过LPCVD工艺在第一氮氧化物层上形成低氧化物层。 第二氮化物层和上氧化物层形成在低氧化物层上。 导电层形成在上氧化物层上。 因此，包括第一氧氮化物层，下氧化物层，第二氮化物层，上氧化物层和致密化的第二氧氮化物层的多层电介质层可以具有增加的电容而不具有退化的漏电流特性。

    Non-volatile memory device and method of manufacturing the same
    3.
    发明授权
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07972923B2

    公开(公告)日：2011-07-05

    申请号：US11605317

    申请日：2006-11-29

    申请人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    发明人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

    摘要翻译： 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层，设置在衬底的表面部分中以限定有源区的场绝缘图案，每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构，以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。

    Non-volatile memory device and method of manufacturing the same
    4.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20080105915A1

    公开(公告)日：2008-05-08

    申请号：US11605317

    申请日：2006-11-29

    申请人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    发明人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

    摘要翻译： 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层，设置在衬底的表面部分中以限定有源区的场绝缘图案，每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构，以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。