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公开(公告)号:US20170243886A1
公开(公告)日:2017-08-24
申请号:US15592030
申请日:2017-05-10
申请人: Jung Hoon LEE , Keejeong RHO , Sejun PARK , Jinhyun SHIN , Dong-Sik LEE , Woong-Seop LEE
发明人: Jung Hoon LEE , Keejeong RHO , Sejun PARK , Jinhyun SHIN , Dong-Sik LEE , Woong-Seop LEE
IPC分类号: H01L27/11582 , G11C16/08 , H01L23/528
CPC分类号: H01L27/11582 , G11C16/08 , H01L23/528 , H01L27/11556 , H01L27/1157
摘要: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.