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    Semiconductor devices including gate insulation layers on channel materials
    2.
    发明授权
    Semiconductor devices including gate insulation layers on channel materials 有权
    半导体器件包括通道材料上的栅极绝缘层

    公开(公告)号：US09553105B2

    公开(公告)日：2017-01-24

    申请号：US14995845

    申请日：2016-01-14

    申请人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/11 ,  H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42352 ,  H01L29/66833

    摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

    摘要翻译： 提供半导体器件。 半导体器件包括交替绝缘层和栅电极的堆叠。 半导体器件包括在堆叠中的通道凹槽中的沟道材料。 半导体器件在通道凹槽中包括在沟道材料上的电荷存储结构。 此外，半导体器件在沟道材料上包括栅极绝缘层。 栅极绝缘层将沟道材料的一部分切下。 还提供了形成半导体器件的相关方法。

    SEMICONDUCTOR DEVICES INCLUDING GATE INSULATION LAYERS ON CHANNEL MATERIALS AND METHODS OF FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING GATE INSULATION LAYERS ON CHANNEL MATERIALS AND METHODS OF FORMING THE SAME 有权
    在通道材料上包括门绝缘层的半导体器件及其形成方法

    公开(公告)号：US20160268302A1

    公开(公告)日：2016-09-15

    申请号：US14995845

    申请日：2016-01-14

    申请人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42352 ,  H01L29/66833

    摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

    摘要翻译： 提供半导体器件。 半导体器件包括交替绝缘层和栅电极的叠层。 半导体器件包括在堆叠中的通道凹槽中的沟道材料。 半导体器件在通道凹槽中包括在沟道材料上的电荷存储结构。 此外，半导体器件在沟道材料上包括栅极绝缘层。 栅极绝缘层将沟道材料的一部分切下。 还提供了形成半导体器件的相关方法。

    VERTICAL MEMORY DEVICES
    5.
    发明申请
    VERTICAL MEMORY DEVICES 有权
    垂直存储器件

    公开(公告)号：US20160268301A1

    公开(公告)日：2016-09-15

    申请号：US14988178

    申请日：2016-01-05

    申请人： Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

    摘要翻译： 垂直存储器件包括衬底，栅极线，沟道，触点和接触间隔物。 栅极线在衬底上堆叠在彼此的顶部。 栅极线相对于衬底的顶表面在垂直方向上彼此间隔开。 栅极线包括相对于衬底的顶表面在平行方向上延伸的台阶部分。 通道沿垂直方向延伸穿过栅极线。 触点位于栅极线的台阶上。 接触垫片选择性地沿接触部分的侧壁形成。

    VERTICAL MEMORY DEVICES
    6.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开
    垂直存储器件

    公开(公告)号：US20170062473A1

    公开(公告)日：2017-03-02

    申请号：US15349625

    申请日：2016-11-11

    申请人： Byung-Jin LEE ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Byung-Jin LEE ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

    摘要翻译： 垂直存储器件包括衬底，栅极线，沟道，触点和接触间隔物。 栅极线在衬底上堆叠在彼此的顶部。 栅极线相对于衬底的顶表面在垂直方向上彼此间隔开。 栅极线包括相对于衬底的顶表面在平行方向上延伸的台阶部分。 通道沿垂直方向延伸穿过栅极线。 触点位于栅极线的台阶上。 接触垫片选择性地沿接触部分的侧壁形成。

    Vertical memory devices
    7.
    发明授权
    Vertical memory devices 有权
    垂直存储器件

    公开(公告)号：US09524983B2

    公开(公告)日：2016-12-20

    申请号：US14988178

    申请日：2016-01-05

    申请人： Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

    摘要翻译： 垂直存储器件包括衬底，栅极线，沟道，触点和接触间隔物。 栅极线在衬底上堆叠在彼此的顶部。 栅极线相对于衬底的顶表面在垂直方向上彼此间隔开。 栅极线包括相对于衬底的顶表面在平行方向上延伸的台阶部分。 通道沿垂直方向延伸穿过栅极线。 触点位于栅极线的台阶上。 接触垫片选择性地沿接触部分的侧壁形成。

    VERTICAL MEMORY DEVICES
    8.
    发明申请
    VERTICAL MEMORY DEVICES 有权
    垂直存储器件

    公开(公告)号：US20160268264A1

    公开(公告)日：2016-09-15

    申请号：US15001877

    申请日：2016-01-20

    申请人： Sung-Min Hwang ,  Jee-Yong Kim ,  Dae-Seok Byeon

    发明人： Sung-Min Hwang ,  Jee-Yong Kim ,  Dae-Seok Byeon

    IPC分类号： H01L27/115 ,  H01L23/535

    CPC分类号： H01L27/115 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

    摘要翻译： 垂直存储器件包括分别在基本上垂直于衬底的顶表面的垂直方向上彼此间隔开的多个电平的多个栅极电极，在衬底上沿垂直方向延伸并穿透 栅极电极和沿垂直方向延伸并与栅电极接触的多个接触插塞。 至少一个第二接触插塞形成在多个栅电极之间的第一栅电极上，并且在垂直方向上延伸。

    Resistive memory device and operating method
    9.
    发明授权
    Resistive memory device and operating method 有权
    电阻式存储器件及操作方法

    公开(公告)号：US09355721B2

    公开(公告)日：2016-05-31

    申请号：US14800727

    申请日：2015-07-16

    申请人： Chi-Weon Yoon ,  Hyun-Kook Park ,  Dae-Seok Byeon

    发明人： Chi-Weon Yoon ,  Hyun-Kook Park ,  Dae-Seok Byeon

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0092

    摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

    摘要翻译： 操作存储器件的方法包括： 通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中 所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压 在第二设定写入间隔期间到第一信号线的第二电压。

    Flash memory device operating at multiple speeds
    10.
    发明授权
    Flash memory device operating at multiple speeds 有权
    闪存设备以多种速度运行

    公开(公告)号：US07957201B2

    公开(公告)日：2011-06-07

    申请号：US12854987

    申请日：2010-08-12

    申请人： Dae-Seok Byeon

    发明人： Dae-Seok Byeon

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/30 ,  G11C16/24

    摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

    摘要翻译： 操作闪速存储器件的方法包括具有不同操作速度的第一操作模式和第二操作模式。 第一和第二操作模式中的每一个包括位线建立间隔和至少一个附加间隔。 闪存被分成连接到相应的第一和第二R / W电路的第一和第二垫。 在第二操作模式的位线设置间隔期间，闪速存储器以时分方式控制第一和第二R / W电路的操作，以交错第一和第二垫的相应的峰值电流间隔。