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公开(公告)号:US10991673B2
公开(公告)日:2021-04-27
申请号:US16591797
申请日:2019-10-03
发明人: Yoichiro Kurita
IPC分类号: H01L25/065 , H01L23/498 , G11C5/04 , G06N3/04 , H01L25/10
摘要: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
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公开(公告)号:US10475767B2
公开(公告)日:2019-11-12
申请号:US16029194
申请日:2018-07-06
发明人: Yoichiro Kurita
IPC分类号: H01L25/065 , G06N3/04
摘要: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
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公开(公告)号:US10396060B2
公开(公告)日:2019-08-27
申请号:US15904201
申请日:2018-02-23
发明人: Yoichiro Kurita , Hideto Furuyama , Hiroshi Uemura
摘要: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
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公开(公告)号:US11239145B2
公开(公告)日:2022-02-01
申请号:US16808522
申请日:2020-03-04
发明人: Yoichiro Kurita , Hideto Furuyama
IPC分类号: H01L23/52 , H01L23/498 , H01L23/00 , H01L23/32
摘要: According to one embodiment, the electrode pads are provided at a surface of the substrate. The metal pad is provided at the surface of the substrate. The electronic component is mounted to the surface of the substrate. The electronic component includes a plurality of opposing electrodes. The opposing electrodes oppose the electrode pads in a direction toward the surface direction and are electrically connected to the electrode pads. The positioning component is fixed to the metal pad. A gap between the positioning component and the electronic component in an in-plane direction of the surface of the substrate is shorter than a minimum distance of the electrode pads.
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公开(公告)号:US20170263595A1
公开(公告)日:2017-09-14
申请号:US15257433
申请日:2016-09-06
CPC分类号: H01L25/167 , H01L24/32 , H01L24/83 , H01L24/94 , H01L24/96 , H01L2224/27502 , H01L2224/29186 , H01L2224/32145 , H01L2224/83009 , H01L2224/83203 , H01L2224/83359 , H01L2224/83379 , H01L2224/83896 , H01L2924/10253 , H01L2924/1032
摘要: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.
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公开(公告)号:US09595507B2
公开(公告)日:2017-03-14
申请号:US14839676
申请日:2015-08-28
发明人: Yoichiro Kurita
IPC分类号: H01L25/065 , H01L25/00 , H01L23/498 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/18
CPC分类号: H01L25/0657 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L23/3135 , H01L23/3157 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/13025 , H01L2224/131 , H01L2224/13144 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81065 , H01L2224/81815 , H01L2224/83005 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/10253 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/15313 , H01L2924/18161 , H01L2924/3511 , H01L2924/014 , H01L2924/00014 , H01L2224/83 , H01L2224/81 , H01L2924/00
摘要: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.
摘要翻译: 根据一个实施例,半导体器件包括包括多个半导体芯片并且具有第一宽度的层压体,至少部分半导体芯片包括延伸穿过半导体芯片的电极,半导体芯片被堆叠并彼此连接通过 电极; 设置在所述层压体的第一表面上并且具有大于所述第一宽度的第二宽度的硅基板; 设置在所述层叠体的第二面上的布线层; 以及设置在层叠体周围的树脂。
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公开(公告)号:US10429598B2
公开(公告)日:2019-10-01
申请号:US15265093
申请日:2016-09-14
摘要: According to one embodiment, an optical device includes an optical element and a via. The optical element is provided directly on a second main surface opposed to a first main surface of a semiconductor substrate. The via is aligned with the optical element and formed to extend halfway in a thickness direction from the first main surface of the semiconductor substrate.
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公开(公告)号:US10032758B2
公开(公告)日:2018-07-24
申请号:US15257433
申请日:2016-09-06
摘要: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.
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公开(公告)号:US09728519B2
公开(公告)日:2017-08-08
申请号:US14710070
申请日:2015-05-12
发明人: Yoichiro Kurita
CPC分类号: H01L24/97 , H01L21/02076 , H01L21/67132 , H01L24/75 , H01L24/83 , H01L2224/7525 , H01L2224/753 , H01L2224/7555 , H01L2224/756 , H01L2224/75743 , H01L2224/759 , H01L2224/83104 , H01L2224/832 , H01L2224/838 , H01L2224/97 , H01L2924/05442 , H01L2924/10253 , H01L2924/1032
摘要: According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a semiconductor chip and an activated front surface of a substrate so as to face each other with a back surface of the semiconductor chip attached to a sheet. The bonding method includes pushing the back surface of the semiconductor chip through the sheet to closely attach the activated front surface of the semiconductor chip and the activated front surface of the substrate. The bonding method includes stripping the sheet from the back surface of the semiconductor chip while maintaining a state in which the activated front surface of the semiconductor chip is closely attached to the activated front surface of the substrate.
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公开(公告)号:US11935846B2
公开(公告)日:2024-03-19
申请号:US18310094
申请日:2023-05-01
IPC分类号: H01L23/64 , H01L23/00 , H01L23/31 , H01L23/367
CPC分类号: H01L23/645 , H01L23/3107 , H01L23/367 , H01L24/48 , H01L2224/48227
摘要: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.
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