PHYSICAL VAPOR DEPOSITION CHAMBER WITH CAPACITIVE TUNING AT WAFER SUPPORT
    3.
    发明申请
    PHYSICAL VAPOR DEPOSITION CHAMBER WITH CAPACITIVE TUNING AT WAFER SUPPORT 有权
    具有电容调谐功能的物理蒸气沉积室

    公开(公告)号:US20130008778A1

    公开(公告)日:2013-01-10

    申请号:US13614704

    申请日:2012-09-13

    摘要: In a plasma enhanced physical vapor deposition of a material onto workpiece, a metal target faces the workpiece across a target-to-workpiece gap less than a diameter of the workpiece. A carrier gas is introduced into the chamber and gas pressure in the chamber is maintained above a threshold pressure at which mean free path is less than 5% of the gap. RF plasma source power from a VHF generator is applied to the target to generate a capacitively coupled plasma at the target, the VHF generator having a frequency exceeding 30 MHz. The plasma is extended across the gap to the workpiece by providing through the workpiece a first VHF ground return path at the frequency of the VHF generator.

    摘要翻译: 在等离子体中将材料物理气相沉积到工件上时,金属靶在工件间距小于工件直径的工件间距对象。 将载气引入室中,并且室中的气体压力保持在平均自由程小于间隙的5%的阈值压力以上。 来自VHF发生器的RF等离子体源功率被施加到目标以在目标处产生电容耦合等离子体,VHF发生器具有超过30MHz的频率。 通过在VHF发生器的频率处提供穿过工件的第一VHF接地返回路径,等离子体跨越间隙延伸到工件。

    PROCESS FOR REMOVING HIGH STRESSED FILM USING LF OR HF BIAS POWER AND CAPACITIVELY COUPLED VHF SOURCE POWER WITH ENHANCED RESIDUE CAPTURE
    4.
    发明申请
    PROCESS FOR REMOVING HIGH STRESSED FILM USING LF OR HF BIAS POWER AND CAPACITIVELY COUPLED VHF SOURCE POWER WITH ENHANCED RESIDUE CAPTURE 有权
    使用低频或高频偏置功率移除高压薄膜的过程和具有增强残留捕获能力的电容耦合甚高频源

    公开(公告)号:US20080014747A1

    公开(公告)日:2008-01-17

    申请号:US11626151

    申请日:2007-01-23

    IPC分类号: H01L21/302

    摘要: A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling. Conductive vias are formed in a dielectric layer of the semiconductor wafer, which are then covered with an overlying dielectric layer. High aspect ratio openings are etched through the overlying dielectric layer to the conductive via to expose a face of the conductive via. This step is followed by a preclean step for removing residue from the exposed face of each conductive via while capturing at least a portion of the residue on the roughened interior surface of the lid. This preclean step consists of: (1) placing the wafer on the wafer pedestal of the plasma clean reactor chamber and introducing an inert gas into the preclean reactor chamber; (2) coupling VHF plasma source power of 60 MHz or greater to the wafer pedestal with sufficient power to establish an etch rate on the order of 200-500 Å/min; and (3) coupling LF or HF plasma bias power of 13.56 MHz or less with sufficient power to realize the etch rate at the bottom surfaces of the high aspect ratio openings, and removing the wafer from the plasma clean reactor chamber.

    摘要翻译: 在半导体晶片上制造多层互连结构的方法首先通过将金属盖的内表面粗糙化为超过SA 2000的表面粗糙度而具有折入表面轮廓,并且将金属盖安装为等离子体清洁反应器室的顶部 具有面向天花板内表面的晶片基座。 导电通孔形成在半导体晶片的电介质层中,然后用覆盖的介电层覆盖。 通过上覆电介质层将高纵横比开口蚀刻到导电通孔,以露出导电通孔的表面。 该步骤之后是用于从每个导电通孔的暴露面去除残留物的预清洗步骤,同时捕获盖的粗糙化内表面上的至少一部分残余物。 该预清洗步骤包括:(1)将晶片放置在等离子体清洁反应器室的晶片基座上,并将惰性气体引入预清洗反应器室中; (2)以足够的功率将60MHz或更高的VHF等离子体源功率耦合到晶片基座,以建立约200-500埃/分钟的蚀刻速率; 和(3)以13.56MHz或更小的LF或HF等离子体偏置功率与足够的功率耦合以实现高纵横比开口的底表面处的蚀刻速率,以及从等离子体清洁反应器室中移除晶片。