摘要:
A method and apparatus for forming lithium-ion batteries and battery cell components, and more specifically, to a system and method for fabricating such batteries and battery cell components using deposition processes that form three-dimensional porous structures are provided. One method comprises texturing a conductive substrate by calendering the conductive substrate between opposing wire mesh structures, forming a first layer of cathodically active material having a first porosity on the surface of the textured conductive substrate, and forming a second layer of cathodically active material having a second porosity on the first layer, wherein the second porosity is greater than the first porosity.
摘要:
A method of fabricating multilayer interconnect structures on a semiconductor wafer uses an interior surface of a metal lid that has been roughed to a surface roughness in excess of RA 2000 with a reentrant surface profile. The metal lid is installed as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling.
摘要:
In a plasma enhanced physical vapor deposition of a material onto workpiece, a metal target faces the workpiece across a target-to-workpiece gap less than a diameter of the workpiece. A carrier gas is introduced into the chamber and gas pressure in the chamber is maintained above a threshold pressure at which mean free path is less than 5% of the gap. RF plasma source power from a VHF generator is applied to the target to generate a capacitively coupled plasma at the target, the VHF generator having a frequency exceeding 30 MHz. The plasma is extended across the gap to the workpiece by providing through the workpiece a first VHF ground return path at the frequency of the VHF generator.
摘要:
A method of fabricating multilayer interconnect structures on a semiconductor wafer begins by roughening the interior surface of a metal lid to a surface roughness in excess of SA 2000 with a reentrant surface profile, and installing the metal lid as the ceiling of a plasma clean reactor chamber having a wafer pedestal facing the interior surface of the ceiling. Conductive vias are formed in a dielectric layer of the semiconductor wafer, which are then covered with an overlying dielectric layer. High aspect ratio openings are etched through the overlying dielectric layer to the conductive via to expose a face of the conductive via. This step is followed by a preclean step for removing residue from the exposed face of each conductive via while capturing at least a portion of the residue on the roughened interior surface of the lid. This preclean step consists of: (1) placing the wafer on the wafer pedestal of the plasma clean reactor chamber and introducing an inert gas into the preclean reactor chamber; (2) coupling VHF plasma source power of 60 MHz or greater to the wafer pedestal with sufficient power to establish an etch rate on the order of 200-500 Å/min; and (3) coupling LF or HF plasma bias power of 13.56 MHz or less with sufficient power to realize the etch rate at the bottom surfaces of the high aspect ratio openings, and removing the wafer from the plasma clean reactor chamber.