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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11742032B2

    公开(公告)日：2023-08-29

    申请号：US17583488

    申请日：2022-01-25

    Applicant: KIOXIA CORPORATION

    Inventor： Takeshi Hioka

    IPC: G11C7/00 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

    Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

    Semiconductor storage device acquiring voltage from dummy pillars
    5.
    发明授权
    Semiconductor storage device acquiring voltage from dummy pillars 有权

    公开(公告)号：US12211561B2

    公开(公告)日：2025-01-28

    申请号：US17899951

    申请日：2022-08-31

    Applicant: KIOXIA CORPORATION

    Inventor： Takeshi Hioka

    IPC: G11C16/28 ,  G11C16/04 ,  G11C16/14

    Abstract: A semiconductor storage device includes a plurality of word line layers stacked above one another in a first direction, a memory pillar having a columnar body penetrating the plurality of the word line layers, wherein each portion of the memory pillar intersecting the word line layers functions as a memory cell transistor, a source line layer to which an end of the memory pillar is connected, an acquisition circuit configured to acquire a voltage of the source line layer, and a first adjustment circuit configured to adjust the voltage of the source line layer to a predetermined target voltage based on the acquired voltage. The acquisition circuit includes a dummy pillar having a columnar body penetrating the plurality of word line layers and having an end connected to the source line layer, wherein each portion of the dummy pillar intersecting the word line layers functions as a dummy transistor.

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11527284B2

    公开(公告)日：2022-12-13

    申请号：US17198375

    申请日：2021-03-11

    Applicant: Kioxia Corporation

    Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi ,  Takeshi Hioka

    IPC: G11C11/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

    Semiconductor storage device and reading method thereof
    7.
    发明授权
    Semiconductor storage device and reading method thereof 有权

    公开(公告)号：US11302399B2

    公开(公告)日：2022-04-12

    申请号：US17008337

    申请日：2020-08-31

    Applicant: KIOXIA CORPORATION

    Inventor： Kosuke Yanagidaira ,  Takuyo Kodama ,  Takeshi Hioka

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  H01L27/115

    Abstract: A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11270775B2

    公开(公告)日：2022-03-08

    申请号：US17096127

    申请日：2020-11-12

    Applicant: KIOXIA CORPORATION

    Inventor： Takeshi Hioka

    IPC: G11C11/34 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

    Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11189348B2

    公开(公告)日：2021-11-30

    申请号：US17009389

    申请日：2020-09-01

    Applicant: KIOXIA CORPORATION

    Inventor： Takeshi Hioka ,  Naofumi Abiko ,  Masaki Unno

    IPC: G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

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