公开(公告)号：US11302399B2

公开(公告)日：2022-04-12

申请号：US17008337

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Takuyo Kodama ,  Takeshi Hioka

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  H01L27/115

Abstract: A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.

公开(公告)号：US10861560B2

公开(公告)日：2020-12-08

申请号：US16718032

申请日：2019-12-17

Applicant: KIOXIA CORPORATION

Inventor： Takuyo Kodama

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14 ,  G11C11/56 ,  G11C16/30 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a first word line coupled to the first memory cell; a first sense amplifier including a first transistor; a first bit line which couples the first memory cell to the first transistor; and a first driver configured to supply a first control signal to a gate of the first transistor. The first driver includes a first circuit configured to compare the first control signal and a second control signal to generate a third control signal based on a comparison result.

公开(公告)号：US11183230B2

公开(公告)日：2021-11-23

申请号：US16799196

申请日：2020-02-24

Applicant: KIOXIA CORPORATION

Inventor： Rui Ito ,  Takeshi Hioka ,  Takuyo Kodama

IPC: G11C16/24 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/4094

Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.