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    System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking
    3.
    发明申请
    System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking 有权
    基于半导体晶片卡盘的有限元模型预测面内失真的系统和方法

    公开(公告)号：US20160283625A1

    公开(公告)日：2016-09-29

    申请号：US15172667

    申请日：2016-06-03

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Jaydeep Sinha ,  Haiguang Chen ,  Michael Kirk

    IPC: G06F17/50

    CPC classification number: G06F17/5018 ,  H01L21/67288

    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

    Abstract translation: 公开了用于预测半导体晶片夹持工艺中的晶片形状的面内失真（IPD）的系统和方法。 根据本公开的一个实施例，利用基于IPD预测的非线性有限元（FE）接触力学模型的一系列Zernike基晶片形状处理。 基于模拟的基于有限元模型的预测过程基本上更有效，并且提供了与使用全尺寸3-D晶片和卡盘几何信息的基于有限元模型的基于有限元模型的预测相当的精度，并且需要计算密集模拟。 此外，还公开了基于一系列Zernike基晶片形状图像的增强型HOS IPD / OPD预测处理。

    System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
    4.
    发明授权
    System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking 有权
    系统和方法来模拟基于半导体晶片夹持的面内失真预测的有限元模型

    公开(公告)号：US09430593B2

    公开(公告)日：2016-08-30

    申请号：US13735737

    申请日：2013-01-07

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Jaydeep Sinha ,  Haiguang Chen ,  Michael Kirk

    IPC: G06F17/10 ,  G06F17/50 ,  H01L21/67

    CPC classification number: G06F17/5018 ,  H01L21/67288

    Abstract: Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

    Abstract translation: 公开了用于预测半导体晶片夹持工艺中的晶片形状的面内失真（IPD）的系统和方法。 根据本公开的一个实施例，利用仿真基于IPD预测的非线性有限元（FE）接触力学模型的过程。 基于模拟的基于有限元模型的预测过程基本上更有效，并且提供了与使用全尺寸3-D晶片和卡盘几何信息的基于有限元模型的基于有限元模型的预测相当的精度，并且需要计算密集模拟。 此外，还公开了基于一系列Zernike基晶片形状图像的增强型HOS IPD / OPD预测处理。

    Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry
    9.
    发明申请
    Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry 有权
    使用干涉测量法预测和控制晶片中的关键尺寸问题和图案缺陷

    公开(公告)号：US20160163033A1

    公开(公告)日：2016-06-09

    申请号：US14730997

    申请日：2015-06-04

    Applicant: KLA-Tencor Corporation

    Inventor： Pradeep Vukkadala ,  Sathish Veeraraghavan ,  Soham Dey ,  Jaydeep Sinha

    IPC: G06T7/00 ,  G06K9/62

    CPC classification number: G06T7/0004 ,  G06K9/6201 ,  G06T7/001 ,  G06T2207/10004 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

    Abstract: Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.

    Abstract translation: 公开了使用图案化晶片几何（PWG）测量在图案化晶片中预测和控制图案质量数据（例如临界尺寸和/或图案缺陷率）的系统和方法。 可以建立PWG测量和模式质量数据测量之间的相关性，并且可以利用所建立的相关性来基于为给定晶片获得的几何测量来为给定晶片提供图案质量数据预测。 可以将所产生的预测提供给光刻工具，光刻工具可以利用预测来校正可能在光刻工艺期间发生的焦点和/或标题误差。

    Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control
    10.
    发明授权
    Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control 有权

    公开(公告)号：US10509329B2

    公开(公告)日：2019-12-17

    申请号：US14597062

    申请日：2015-01-14

    Applicant: KLA-Tencor Corporation

    Inventor： Sathish Veeraraghavan ,  Chin-Chou Huang

    IPC: G03F7/20

    Abstract: Systems and methods for providing improved measurements and predictions of geometry induced overlay errors are disclosed. Information regarding variations of overlay errors is obtained and analyzed to improve semiconductor processes as well as lithography patterning. In some embodiments, a cascading analysis process is utilized to breakdown the wafer geometry induced overlay into various components. The breakdown analysis may also be utilized to determine effectiveness factors for the various components, which in turn may improve the prediction accuracy of the impact of wafer geometry on wafer overlay. Furthermore, the measurements and/or predictions of the wafer geometry induced overlay errors may be utilized to provide overlay monitoring and correction solutions.

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