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    Common electronic dispersion compensation arrangement for use with multiple optical communication channels
    4.
    发明授权
    Common electronic dispersion compensation arrangement for use with multiple optical communication channels 有权
    通用电子色散补偿布置，用于多个光通信通道

    公开(公告)号：US07570889B2

    公开(公告)日：2009-08-04

    申请号：US11413675

    申请日：2006-04-27

    Applicant: Kalpendu Shastri ,  Bipin Dama ,  David Piede

    Inventor： Kalpendu Shastri ,  Bipin Dama ,  David Piede

    IPC: H04B10/06

    CPC classification number: H04L25/0228 ,  H04B10/66 ,  H04L25/025 ,  H04L25/03057

    Abstract: An electronic dispersion compensation (EDC) arrangement for a multi-channel optical receive utilizes a time division technique to “share” a common adaptive algorithm block between a plurality of N separate channels. The algorithm block embodies a specific algorithm associated with correcting/updating tap weights for the delay lines forming the equalizing elements, and a time slot assignment element is used in conjunction with the algorithm block to control the access of the various channels to the algorithm block. In situations where certain channels experience a greater degree of dispersion than others, the time slot assignment element may be configured to allot a greater number of time slots to the affected channels.

    Abstract translation: 用于多通道光接收的电子色散补偿（EDC）装置利用时分技术“共享”多个N个独立信道之间的公共自适应算法块。 算法块体现了与形成均衡元件的延迟线的校正/更新抽头权重相关联的特定算法，并且时隙分配元件与算法块结合使用以控制各种信道对算法块的访问。 在某些频道经历比其他频道更大程度的色散的情况下，时隙分配元件可以被配置为向受影响的频道分配更多数量的时隙。

    SOI-based optical interconnect arrangement
    5.
    发明申请
    SOI-based optical interconnect arrangement 审中-公开
    基于SOI的光学互连装置

    公开(公告)号：US20060126993A1

    公开(公告)日：2006-06-15

    申请号：US11287114

    申请日：2005-11-25

    Applicant: David Piede ,  Bipin Dama ,  Kalpendu Shastri ,  John Fangman ,  Harvey Wagner ,  Margaret Ghiron

    Inventor： David Piede ,  Bipin Dama ,  Kalpendu Shastri ,  John Fangman ,  Harvey Wagner ,  Margaret Ghiron

    IPC: G02B6/12

    CPC classification number: H04B10/801 ,  G02B6/43

    Abstract: An SOI-based optical interconnection arrangement is provided that significantly reduces the size, complexity and power consumption requires of conventional high density electrical interconnections. In particular, a group of optical modulators and wavelength division multiplexers/demultiplexers are used in association with traditional electrical signal paths to “concentrate” a large number of the electrical-pinouts onto one optical waveguide (e.g., fiber). By utilizing a number of such SOI-based signal concentration structures, an optical backplane can be formed that couples all of these concentration structures through one optical substrate and then onto a separate number of output/receiving boards. Additionally, optical gain material may be embedded within the backplane element to further enhance the optical signal quality. The ability to integrate the electrical and optical components within a monolithic SOI-based structure provides for the significant reduction in the overall size of the connection arrangement and, further, reduces the power consumption by about an order of magnitude.

    Abstract translation: 提供了一种基于SOI的光互连装置，其显着地减小了常规高密度电互连所需的尺寸，复杂性和功耗。 特别地，一组光调制器和波分复用器/解复用器与传统的电信号路径相关联地使用，以将大量的电插座“集中”到一个光波导（例如，光纤）上。 通过利用多个这样的基于SOI的信号浓度结构，可以形成光背板，其通过一个光学基板将所有这些浓度结构耦合到另一数目的输出/接收板上。 此外，光增益材料可以嵌入在背板元件内以进一步增强光信号质量。 将电和光学部件集成在基于单片SOI的结构内的能力提供了连接装置的整体尺寸的显着降低，并且进一步将功耗降低约一个数量级。

    Vertical stacking of multiple integrated circuits including SOI-based optical components
    6.
    发明申请
    Vertical stacking of multiple integrated circuits including SOI-based optical components 审中-公开
    包括基于SOI的光学元件的多个集成电路的垂直堆叠

    公开(公告)号：US20060177173A1

    公开(公告)日：2006-08-10

    申请号：US11346718

    申请日：2006-02-03

    Applicant: Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

    Inventor： Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

    IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/10

    CPC classification number: G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02F1/025 ,  H01L31/12

    Abstract: A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

    Abstract translation: 集成电路的垂直堆叠包括至少一个CMOS电子集成电路（IC），基于SOI的光电集成电路结构以及光输入/输出耦合元件。 可以通过堆叠的厚度形成多个金属化通孔，使得可以在每个集成电路之间进行电连接。 可以使用各种类型的光输入/输出耦合，例如棱镜耦合，光栅，逆锥等。 通过将光学和电气功能分离到单独的IC上，可以修改每个功能，而不需要重新设计剩余的系统。 通过使用具有CMOS电子IC的基于SOI的光电子器件，SOI结构的一部分可能被暴露以提供对波导SOI层的访问以用于光学耦合目的。

    Wafer-level opto-electronic testing apparatus and method
    7.
    发明申请
    Wafer-level opto-electronic testing apparatus and method 有权
    晶圆级光电测试仪器及方法

    公开(公告)号：US20050194990A1

    公开(公告)日：2005-09-08

    申请号：US11075430

    申请日：2005-03-08

    Applicant: Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine Yanushefski

    Inventor： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine Yanushefski

    IPC: G01R31/26

    CPC classification number: G02B6/30 ,  G02B6/34 ,  G02B2006/12107

    Abstract: A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

    Abstract translation: 用于在绝缘体上硅（SOI）晶片结构中形成的光电器件的晶片级测试装置利用单个光电测试元件执行光学和电学测试。 光束转向光学元件可以形成在测试元件上，并且用于促进光学探针信号与形成在SOI结构的顶表面上的光耦合元件（例如，棱镜耦合器，光栅）之间的耦合。 此后，光学测试信号被引导到形成在SOI结构的顶层中的光波导中。 光电测试元件还包括多个电测试引脚，其被定位成接触光电器件上的多个接合焊盘测试点并执行电测试操作。 光学测试信号结果可以转换为SOI结构内的电气表示，并因此作为电信号返回到测试元件。

    EMI-EMC shield for silicon-based optical transceiver
    8.
    发明申请
    EMI-EMC shield for silicon-based optical transceiver 审中-公开
    用于硅基光收发器的EMI-EMC屏蔽

    公开(公告)号：US20050135727A1

    公开(公告)日：2005-06-23

    申请号：US11013722

    申请日：2004-12-16

    Applicant: David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

    Inventor： David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

    IPC: G02B6/42 ,  G02B6/12

    CPC classification number: G02B6/4277 ,  G02B6/42 ,  G02B6/4246 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014

    Abstract: An SOI-based opto-electronic structure includes various electronic components disposed with their associated optical components within a single SOI layer, forming a monolithic arrangement. EMI/EMC shielding is provided by forming a metallized outer layer on the surface of an external prism coupler that interfaces with the SOI layer, the metallized layer including transparent apertures to allow an optical signal to be coupled into and out of the SOI layer. The opposing surface of the prism coupler may also be coated with a metallic material to provide additional shielding. Further, metallic shielding plates may be formed on the SOI structure itself, overlying the locations of EMI-sensitive electronics. All of these metallic layers are ultimately coupled to an external ground plane to isolate the structure and provide the necessary shielding.

    Abstract translation: 基于SOI的光电结构包括在单个SOI层内与其相关联的光学部件一起设置的各种电子部件，形成单片布置。 通过在与SOI层相接的外部棱镜耦合器的表面上形成金属化的外层来提供EMI / EMC屏蔽，金属化层包括透明的孔，以允许光信号耦合到SOI层中。 棱镜耦合器的相对表面也可以用金属材料涂覆以提供额外的屏蔽。 此外，金属屏蔽板可以形成在SOI结构本身上，覆盖EMI敏感电子器件的位置。 所有这些金属层最终被耦合到外部接地平面以隔离结构并提供必要的屏蔽。

    Planar waveguide optical isolator in thin silicon-on-isolator (SOI) structure
    9.
    发明申请
    Planar waveguide optical isolator in thin silicon-on-isolator (SOI) structure 失效
    薄硅隔离器（SOI）结构中的平面波导光隔离器

    公开(公告)号：US20050123232A1

    公开(公告)日：2005-06-09

    申请号：US11005286

    申请日：2004-12-06

    Applicant: David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski ,  Harvey Wagner

    Inventor： David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski ,  Harvey Wagner

    IPC: G02B20060101 ,  G02B6/122 ,  G02B6/125 ,  G02B6/26 ,  G02B6/42

    CPC classification number: G02B6/1228 ,  G02B6/125 ,  G02B6/4207

    Abstract: A planar optical isolator is formed within the silicon surface layer of an SOI structure. A forward-directed signal is applied to an input waveguiding section of the isolator and thereafter propagates through a non-reciprocal waveguide coupling region into an output waveguide section. A rearward-directed signal enters via the output waveguide section and is thereafter coupled into the non-reciprocal waveguide structure, where the geometry of the structure functions to couple only a small amount of the reflected signal into the input waveguide section. In one embodiment, the non-reciprocal structure comprises an N-way directional coupler (with one output waveguide, one input waveguide and N-1 isolating waveguides). In another embodiment, the non-reciprocal structure comprises a waveguide expansion region including a tapered, mode-matching portion coupled to the output waveguide and an enlarged, non-mode matching portion coupled to the input waveguide such that a majority of a reflected signal will be mismatched with respect to the input waveguide section. By cascading a number of such planar SOI-based structures, increased isolation can be achieved—advantageously within a monolithic arrangement.

    Abstract translation: 在SOI结构的硅表面层内形成平面光隔离器。 正向信号被施加到隔离器的输入波导部分，然后通过非互易波导耦合区域传播到输出波导部分中。 后向信号经由输出波导部分进入，然后耦合到不可逆波导结构中，其中结构的几何结构仅将少量的反射信号耦合到输入波导部分中。 在一个实施例中，非互易结构包括N路定向耦合器（具有一个输出波导，一个输入波导和N-1个隔离波导）。 在另一个实施例中，不可逆结构包括波导扩展区域，其包括耦合到输出波导的锥形模式匹配部分和耦合到输入波导的放大的非模式匹配部分，使得反射信号的大部分将 相对于输入波导部分不匹配。 通过级联多个这种平面的基于SOI的结构，可以实现增加的隔离 - 有利地在单片布置中。

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