摘要:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.
摘要:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
摘要:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
摘要:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.
摘要:
An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.
摘要:
A set of interlocking modules supports and connects a die containing lasers, a set of precision molded lenses and a set of beam switching elements. Another embodiment of the invention is a structure for mounting a logic chip and an optical chip on a chip carrier, with the optical chip being mounted on the side of the carrier facing the system board on which the carrier is mounted, so that radiation travels in a straight path from optical sources on the optical chip into optical transmission guides on the board.
摘要:
A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.
摘要:
Disclosed is an aluminum nitride body having graded metallurgy and a method for making such a body. The aluminum nitride body has at least one via and includes a first layer in direct contact with the aluminum nitride body and a second layer in direct contact with, and that completely encapsulates, the first layer. The first layer includes 30 to 60 volume percent aluminum nitride and 40 to 70 volume percent tungsten and/or molybdenum while the second layer includes 90 to 100 volume percent of tungsten and/or molybdenum and 0 to 10 volume percent of aluminum nitride.
摘要:
An unsintered aluminum nitride body including:(a) 1 to 5 weight percent of a vitreous solid of boria, alumina, and calcia in the proportions of (1) boria between 3 and 25 weight percent, (2) alumina between 10 and 50 weight percent, and (3) calcia between 40 and 80 weight percent; and(b) aluminum nitride powder as the balance of the aluminum nitride body.The invention further relates to a method of forming the unsintered aluminum nitride body and then sintering it at a temperature between 1550 and 1650 degrees Centrigrade so as to form a dense, thermally conductive aluminum nitride body.
摘要:
An unsintered aluminum nitride body including:(a) 1 to 5 weight percent of a vitreous solid of boria, alumina, and calcia in the proportions of (1) boria between 3 and 25 weight percent, (2) alumina between 10 and 50 weight percent, and (3) calcia between 40 and 80 weight percent; and(b) aluminum nitride powder as the balance of the aluminum nitride body.