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1.发明授权Measurement methodology and array structure for statistical stress and test of reliabilty structures 失效统计应力的测量方法和阵列结构以及可靠性结构的测试公开(公告)号：US08120356B2
公开(公告)日：2012-02-21
申请号：US12482999
申请日：2009-06-11
IPC分类号： G01V3/00
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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2.发明申请MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效统计应力的测量方法和阵列结构和可靠性结构测试公开(公告)号：US20100318313A1
公开(公告)日：2010-12-16
申请号：US12482999
申请日：2009-06-11
CPC分类号： G01R31/2621 , G01R31/318511
摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.
摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。
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3.发明授权公开(公告)号：US07868640B2
公开(公告)日：2011-01-11
申请号：US12061077
申请日：2008-04-02
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。
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4.发明申请公开(公告)号：US20090251167A1
公开(公告)日：2009-10-08
申请号：US12061077
申请日：2008-04-02
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/3004
摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.
摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。
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公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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7.发明申请RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS 有权可靠性评估和系统故障警告使用芯片参数监视器的方法公开(公告)号：US20120105240A1
公开(公告)日：2012-05-03
申请号：US13344178
申请日：2012-01-05
申请人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
发明人： Jeanne P. Bickford , John R. Goss , Nazmul Habib , Robert McMahon
CPC分类号： G06F17/5045 , G01R31/2894
摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。
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8.发明授权HDL design structure for integrating test structures into an integrated circuit design 有权用于将测试结构集成到集成电路设计中的HDL设计结构公开(公告)号：US07884599B2
公开(公告)日：2011-02-08
申请号：US12106361
申请日：2008-04-21
申请人： Nazmul Habib , Robert McMahon , Troy Perry
发明人： Nazmul Habib , Robert McMahon , Troy Perry
IPC分类号： G01R31/28
CPC分类号： G01R31/31723 , G01R31/31724 , G01R31/318511
摘要： A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.
摘要翻译： 一种硬件描述语言（HDL）设计结构，用于在集成电路上执行特定于设备的测试和获取参数数据，使得每个芯片可以单独测试，而不需要过多的测试时间要求，附加的硅或特殊测试设备。 HDL设计结构包括集成到IC设计中的至少一个设备测试结构的功能表示，该设计测试与IC中包含的所选设备集相同或几乎相同的一组虚拟设备。 测试结构根据客户要求和设计要求从被测器件（DUT）库集成。 所选测试结构的功能表示进一步优先排列，并按优先级顺序分配给设计中的设计元素。 放置算法使用设计，布局和制造要求将测试结构的选定功能表示放置在设计的最终布局中。
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9.发明授权Circuit and method using distributed phase change elements for across-chip temperature profiling 有权使用分布式相变元件进行跨芯片温度分析的电路和方法公开(公告)号：US07882455B2
公开(公告)日：2011-02-01
申请号：US12117784
申请日：2008-05-09
IPC分类号： G06F17/50
摘要： Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconductor chip. These phase change elements are programmed to have essentially the same amorphous resistance. Temperature-dependent behavior exhibited by each of the phase change elements individually is compared to a reference (e.g., generated by a discrete reference phase change element, generated by another one of the phase change elements, or generated by an external reference) in order to profile the temperature gradient across the semiconductor chip. Once profiled, this temperature gradient can be used to redesign and/or relocate functional cores, to set stress limits for qualification of functional cores and/or to adjust operating specifications of functional cores.
摘要翻译： 公开了一种跨芯片温度感测电路及其相关方法，可用于对片内温度梯度进行分析。 这些实施例结合了大致均匀分布在半导体芯片上的多个相变元件。 这些相变元件被编程为具有基本上相同的无定形电阻。 每个相变元件单独表现出的温度相关行为与参考（例如，由离散参考相变元件产生，由另一个相变元件产生或由外部参考产生）相比较，以便 描述半导体芯片上的温度梯度。 一旦进行了分析，该温度梯度可用于重新设计和/或重新定位功能核心，为功能核心的鉴定和/或调整功能核心的操作规范设定应力限制。
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10.发明申请公开(公告)号：US20090210201A1
公开(公告)日：2009-08-20
申请号：US12031079
申请日：2008-02-14
CPC分类号： G06F17/505 , G01R31/3008 , G06F17/5068 , H01L22/34
摘要： A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.
摘要翻译： 一种用于预测和控制泄漏的方法，其中将IDDQ预测宏放置在多个设计拓扑中，并且使用IDDQ预测宏来收集数据。 IDDQ预测宏被配置为使用IDDQ预测宏来测量半导体测试位置和划线中的至少一种设备类型的亚阈值泄漏和栅极泄漏并建立泄漏模型。 该方法将半导体测试现场测量和划线测量相关联，以建立划线控制限制，预测产品泄漏; 并使用泄漏模型为每个产品设置亚阈值泄漏限值和门泄漏限值。
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