MULTI-WIRE PERMUTED FORWARD ERROR CORRECTION

    公开(公告)号:US20220321255A1

    公开(公告)日:2022-10-06

    申请号:US17845638

    申请日:2022-06-21

    申请人: Kandou Labs, S.A.

    摘要: Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.

    Pipelined forward error correction for vector signaling code channel

    公开(公告)号:US10666297B2

    公开(公告)日:2020-05-26

    申请号:US15954138

    申请日:2018-04-16

    申请人: Kandou Labs, S.A.

    摘要: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

    High speed communications system
    5.
    发明授权

    公开(公告)号:US10608850B2

    公开(公告)日:2020-03-31

    申请号:US16537507

    申请日:2019-08-09

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/03 H04L25/49 H04L1/00

    摘要: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.

    Skew-resistant multi-wire channel

    公开(公告)号:US10573998B2

    公开(公告)日:2020-02-25

    申请号:US16216254

    申请日:2018-12-11

    申请人: Kandou Labs, S.A.

    摘要: Methods and systems described include a first dielectric material having a plurality of embedded conductors of a multi-wire channel, the plurality of embedded conductors comprising at least a first, second and third conductor, wherein a first distance between the first and second conductors is less than a second distance between the first and third conductors, wherein the first dielectric material has a first dielectric constant ε1 and a second dielectric material embedded in the first dielectric material, the second dielectric material embedded in between the first and third conductors, the second dielectric material having a second dielectric constant ε2, wherein ε2>ε1.

    CLOCK-EMBEDDED VECTOR SIGNALING CODES
    7.
    发明申请

    公开(公告)号:US20190363916A1

    公开(公告)日:2019-11-28

    申请号:US16533592

    申请日:2019-08-06

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/49 H04L25/08 H04L25/03

    摘要: Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

    QUADRATURE AND DUTY CYCLE ERROR CORRECTION IN MATRIX PHASE LOCK LOOP

    公开(公告)号:US20190182024A1

    公开(公告)日:2019-06-13

    申请号:US16268307

    申请日:2019-02-05

    申请人: Kandou Labs, S.A.

    摘要: Generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

    HIGH SPEED COMMUNICATIONS SYSTEM
    10.
    发明申请

    公开(公告)号:US20190068414A1

    公开(公告)日:2019-02-28

    申请号:US16175800

    申请日:2018-10-30

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/03 H04L25/49 H04L1/00

    摘要: Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.