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103 条记录 (耗时 0.026 秒)

    Junctionless transistor
    1.
    发明授权
    Junctionless transistor 有权
    无结晶体晶体管

    公开(公告)号：US08803233B2

    公开(公告)日：2014-08-12

    申请号：US13242861

    申请日：2011-09-23

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    IPC分类号： H01L29/778

    CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

    摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

    摘要翻译： 晶体管包括半导体层，并且在半导体层上形成栅极电介质。 栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。 有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。 该渐变掺杂剂区域的掺杂浓度逐渐降低。 晶体管还包括与有源区相邻的源区和漏区。 源极和漏极区域和有源区域具有相同的导电类型。

    Junction field effect transistor with an epitaxially grown gate structure
    5.
    发明授权
    Junction field effect transistor with an epitaxially grown gate structure 失效
    具有外延生长栅极结构的结型场效应晶体管

    公开(公告)号：US08435845B2

    公开(公告)日：2013-05-07

    申请号：US13080690

    申请日：2011-04-06

    申请人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L21/337

    CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

    摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure
    6.
    发明申请
    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure 失效
    具有外延生长门结构的结场效应晶体管

    公开(公告)号：US20120256238A1

    公开(公告)日：2012-10-11

    申请号：US13080690

    申请日：2011-04-06

    申请人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/808 ,  H01L21/337

    CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

    摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

    SOI CMOS structure having programmable floating backplate
    9.
    发明授权
    SOI CMOS structure having programmable floating backplate 有权
    具有可编程浮动背板的SOI CMOS结构

    公开(公告)号：US09379028B2

    公开(公告)日：2016-06-28

    申请号：US12619285

    申请日：2009-11-16

    申请人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

    发明人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

    IPC分类号： H01L29/94 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7841

    摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

    摘要翻译： 提供具有至少一个可编程电浮动背板的SOI CMOS结构。 每个电浮动背板均可单独编程。 可以通过将电子注入每个导电浮动背板来进行编程。 编程的擦除可以通过将电子穿过浮动背板来实现。 两个装置中的至少一个可以完成电浮动背栅的编程。 这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。 使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

    SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE
    10.
    发明申请
    SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
    具有可编程浮动背板的SOI CMOS结构

    公开(公告)号：US20130015912A1

    公开(公告)日：2013-01-17

    申请号：US13612036

    申请日：2012-09-12

    申请人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

    发明人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

    IPC分类号： G05F3/02

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7841

    摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

    摘要翻译： 提供具有至少一个可编程电浮动背板的SOI CMOS结构。 每个电浮动背板均可单独编程。 可以通过将电子注入每个导电浮动背板来进行编程。 编程的擦除可以通过将电子穿过浮动背板来实现。 两个装置中的至少一个可以完成电浮动背栅的编程。 这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。 使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。