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公开(公告)号：US07705386B2
公开(公告)日：2010-04-27
申请号：US11969989
申请日：2008-01-07
IPC分类号： H01L27/108 , H01L21/8244
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。
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公开(公告)号：US20090173980A1
公开(公告)日：2009-07-09
申请号：US11969989
申请日：2008-01-07
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。
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3.发明授权公开(公告)号：US07923815B2
公开(公告)日：2011-04-12
申请号：US11969986
申请日：2008-01-07
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。
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4.发明申请TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开具有仅一个方向的横向延伸的TRENCH电容器及相关方法公开(公告)号：US20070267671A1
公开(公告)日：2007-11-22
申请号：US11383861
申请日：2006-05-17
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.
摘要翻译： 公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。 在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。 横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。
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公开(公告)号：US20090174031A1
公开(公告)日：2009-07-09
申请号：US11969986
申请日：2008-01-07
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。
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6.发明授权公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。
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公开(公告)号：US06194736B1
公开(公告)日：2001-02-27
申请号：US09213674
申请日：1998-12-17
申请人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
发明人： Susan E. Chaloux , Tze-Chiang Chen , Johnathan E. Faltermeier , Ulrike Gruening , Rajarao Jammy , Jack A. Mandelman , Christopher C. Parks , Paul C. Parries , Paul A. Ronsheim , Yun-Yu Wang
IPC分类号： H01L2906
CPC分类号： H01L29/66181 , H01L21/02667 , H01L21/2022 , H01L27/10867
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
摘要翻译： 通过产生和使用量子传导重结晶阻挡层，能够实现提高可靠性和/或增加组合选择的缩小结构。 量子导电层优选用于沟槽电容器中以用作再结晶屏障。
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公开(公告)号：US20100207245A1
公开(公告)日：2010-08-19
申请号：US12689501
申请日：2010-01-19
CPC分类号： H01L28/40 , H01L21/7682 , H01L21/76831 , H01L27/10861 , H01L29/66181
摘要： An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
摘要翻译： 公开了一种改进的沟槽结构及其制造方法。 本发明的实施例提供了一种沟槽，其中套环部分具有气隙而不是固体氧化物套环。 气隙提供较低的介电常数。 因此，本发明的实施例可以用于制造更高性能的装置（由于减小的寄生泄漏）或更小的装置，这是由于能够使用更薄的套环来获得与仅由氧化物构成的更厚的套圈相同的性能 没有气隙）。 或者，根据应用，可以进行设计选择以实现改进的性能和减小的尺寸的组合。
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9.发明授权Device structure, layout and fabrication method for uniaxially strained transistors 有权单轴应变晶体管的器件结构，布局和制造方法公开(公告)号：US08288218B2
公开(公告)日：2012-10-16
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。
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10.发明申请HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权具有改进的PFET阈值电压的高K /金属栅极CMOS FINFET公开(公告)号：US20110108920A1
公开(公告)日：2011-05-12
申请号：US12614906
申请日：2009-11-09
申请人： VEERARAGHAVAN S. BASKER , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： VEERARAGHAVAN S. BASKER , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.
摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。
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