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1.发明申请公开(公告)号：US20130019132A1
公开(公告)日：2013-01-17
申请号：US13183471
申请日：2011-07-15
申请人： Karen AMIRKHANYAN , Hayk Grigoryan , Gurgen Harutyunyan , Tatevik Melkumyan , Samvel Shoukourian , Alex Shubat , Valery Vardanian , Yervant Zorian
发明人： Karen AMIRKHANYAN , Hayk Grigoryan , Gurgen Harutyunyan , Tatevik Melkumyan , Samvel Shoukourian , Alex Shubat , Valery Vardanian , Yervant Zorian
IPC分类号： G11C29/10 , G06F11/263
摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.
摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。
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2.发明授权公开(公告)号：US08850277B2
公开(公告)日：2014-09-30
申请号：US13183471
申请日：2011-07-15
申请人： Karen Amirkhanyan , Hayk Grigoryan , Gurgen Harutyunyan , Tatevik Melkumyan , Samvel Shoukourian , Alex Shubat , Valery Vardanian , Yervant Zorian
发明人： Karen Amirkhanyan , Hayk Grigoryan , Gurgen Harutyunyan , Tatevik Melkumyan , Samvel Shoukourian , Alex Shubat , Valery Vardanian , Yervant Zorian
摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.
摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。
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3.发明授权公开(公告)号：US09053050B2
公开(公告)日：2015-06-09
申请号：US13310479
申请日：2011-12-02
CPC分类号： G06F11/1048
摘要： A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
摘要翻译： 基于用于存储器的加扰信息来确定用于多段单纠错（SEC）编码方案的段的期望数量。 期望数量的段可以是满足掩蔽的写分割要求和多位不匹配大小要求所需的最小段数。 在一个方面，存储器加扰信息可以指定存储器采用的不同的加扰技术（例如，输入 - 输出（IO）信元加扰，列加扰，列扭转，带分配等）。 基于加扰信息，可以导出存储器的逻辑结构和物理布局之间的映射。 该映射可用于确定满足掩蔽写入要求和多位不匹配大小要求所需的最少段数。
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4.发明申请公开(公告)号：US20130145119A1
公开(公告)日：2013-06-06
申请号：US13310479
申请日：2011-12-02
IPC分类号： G06F12/10
CPC分类号： G06F11/1048
摘要： A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
摘要翻译： 基于用于存储器的加扰信息确定用于多段单纠错（SEC）编码方案的段的期望数量。 期望数量的段可以是满足掩蔽的写分割要求和多位不匹配大小要求所需的最小段数。 在一个方面，存储器加扰信息可以指定存储器采用的不同的加扰技术（例如，输入 - 输出（IO）信元加扰，列加扰，列扭转，带分配等）。 基于加扰信息，可以导出存储器的逻辑结构和物理布局之间的映射。 该映射可用于确定满足掩蔽写入要求和多位不匹配大小要求所需的最少段数。
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