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    BACKPLANES FOR DISPLAY APPLICATIONS, AND COMPONENTS FOR USE THEREIN
    4.
    发明申请
    BACKPLANES FOR DISPLAY APPLICATIONS, AND COMPONENTS FOR USE THEREIN 有权
    显示应用的背板及其使用的组件

    公开(公告)号：US20070035532A1

    公开(公告)日：2007-02-15

    申请号：US11461255

    申请日：2006-07-31

    申请人： Karl Amundson ,  Yu Chen ,  Kevin Denis ,  Paul Drzaic ,  Peter Kazlas ,  Andrew Ritenour

    发明人： Karl Amundson ,  Yu Chen ,  Kevin Denis ,  Paul Drzaic ,  Peter Kazlas ,  Andrew Ritenour

    IPC分类号： G09G5/00

    CPC分类号： H01L27/12 ,  G09G3/2011 ,  G09G3/344 ,  G09G2300/043 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0209 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/41733 ,  H01L29/42384

    摘要： A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts. The unit includes a transistor, a pixel electrode, a source line and a balance line. The invention also provides a driver for driving a display provided with such a balance line.

    摘要翻译： 薄膜晶体管包括具有第一栅电极边缘和与第一栅电极边缘相对的第二栅电极边缘的栅电极。 TFT还包括具有与第一栅电极边缘重叠的第一漏电极边缘和与第二栅极边缘重叠的第二漏电极边缘的漏电极。 用于制造用于显示器的二极管阵列的方法包括：与衬底相邻的导电层的沉积，与衬底相邻的掺杂半导体层的沉积以及与衬底相邻的未掺杂的半导体层的沉积。 显示像素单元在像素电极和源极线之间提供减小的电容耦合。 该单元包括晶体管，像素电极和源极线。 源极线包括提供晶体管源极的扩展。 图案化导电部分邻近源极线设置。 另一显示像素单元提供减小的像素电极电压偏移。 该单元包括晶体管，像素电极，源极线和平衡线。 本发明还提供一种用于驱动具有这种平衡线的显示器的驱动器。

    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING
    5.
    发明申请
    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 有权
    具有非穿孔半导体通道的半导体器件具有增强导电性和制造方法

    公开(公告)号：US20090278137A1

    公开(公告)日：2009-11-12

    申请号：US12170599

    申请日：2008-07-10

    申请人： David C. Sheridan ,  Andrew Ritenour

    发明人： David C. Sheridan ,  Andrew Ritenour

    IPC分类号： H01L29/24

    CPC分类号： H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7832 ,  H01L29/8083 ,  H01L29/8122

    摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

    摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

    Method for forming an interface between germanium and other materials
    6.
    发明申请
    Method for forming an interface between germanium and other materials 审中-公开
    在锗和其他材料之间形成界面的方法

    公开(公告)号：US20060099782A1

    公开(公告)日：2006-05-11

    申请号：US11251089

    申请日：2005-10-14

    申请人： Andrew Ritenour

    发明人： Andrew Ritenour

    IPC分类号： H01L21/22 ,  H01L21/38

    CPC分类号： H01L21/28255 ,  H01L21/02112 ,  H01L21/314 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    摘要： Interfaces that are portions of semiconductor structures used in integrated circuits and optoelectronic devices are described. In one instance, the semiconductor structure has an interface including a semiconductor surface, an interfacial layer including sulfur, and an electrically active layer (e.g., a dielectric or a metal). Such an interface can inhibit oxidation and improve the carrier mobility of the semiconductor structures in which such an interface is incorporated. The interfacial layer can be created by exposure of the semiconductor surface to sulfur donating compounds (e.g., H2S or SF6) and, optionally, heating.

    摘要翻译： 描述了作为在集成电路和光电子器件中使用的半导体结构的部分的接口。 在一种情况下，半导体结构具有包括半导体表面，包括硫的界面层和电活性层（例如电介质或金属）的界面。 这种界面可以抑制氧化并提高掺入这种界面的半导体结构的载流子迁移率。 界面层可以通过将半导体表面暴露于供硫化合物（例如H 2 S或SF 6）和任选地加热来产生。

    Vertical junction field effect transistors with improved thermal characteristics and methods of making
    7.
    发明授权
    Vertical junction field effect transistors with improved thermal characteristics and methods of making 有权
    具有改进的热特性和制造方法的垂直结型场效应晶体管

    公开(公告)号：US08884270B2

    公开(公告)日：2014-11-11

    申请号：US13436159

    申请日：2012-03-30

    申请人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

    发明人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

    IPC分类号： H01L29/06 ,  H01L29/808 ,  H01L29/40 ,  H01L29/66

    CPC分类号： H01L29/8083 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/66909

    摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.

    摘要翻译： 描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。 电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

    Methods of making semiconductor devices having implanted sidewalls and devices made thereby
    8.
    发明授权
    Methods of making semiconductor devices having implanted sidewalls and devices made thereby 有权
    制造具有植入侧壁的半导体器件的方法和由此制成的器件

    公开(公告)号：US08466017B2

    公开(公告)日：2013-06-18

    申请号：US12962823

    申请日：2010-12-08

    申请人： David C. Sheridan ,  Andrew Ritenour

    发明人： David C. Sheridan ,  Andrew Ritenour

    IPC分类号： H01L21/337

    CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

    摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

    摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。 使用注入掩模使用选择性离子注入制造器件。 器件具有通过从注入掩模中散射正常或接近正常的入射离子而形成的侧壁。 还描述了具有长沟道长度的垂直结型场效应晶体管。 这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。

    Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
    9.
    发明授权
    Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making 有权
    自对准半导体器件在反向偏压下具有减少的栅极源漏极和制造方法

    公开(公告)号：US08659057B2

    公开(公告)日：2014-02-25

    申请号：US13112075

    申请日：2011-05-20

    申请人： Andrew Ritenour ,  David C. Sheridan

    发明人： Andrew Ritenour ,  David C. Sheridan

    IPC分类号： H01L29/15 ,  H01L31/0312

    CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/7722

    摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

    摘要翻译： 描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。 为了保持良好的高电压性能（即低DIBL），器件栅极可以自对准到源极的0.5μm以内，同时在反向偏压下减小栅极 - 源极结泄漏。 该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。 还描述了制造该装置的方法。