公开(公告)号：US20050042538A1

公开(公告)日：2005-02-24

申请号：US10646307

申请日：2003-08-22

申请人： Katherina Babich ,  Elbert Huang ,  Arpan Mahorowala ,  David Medeiros ,  Dirk Pfeiffer ,  Karen Temple

发明人： Katherina Babich ,  Elbert Huang ,  Arpan Mahorowala ,  David Medeiros ,  Dirk Pfeiffer ,  Karen Temple

IPC分类号： G03F7/11 ,  G03F7/00 ,  G03F7/004 ,  G03F7/075 ,  G03F7/09 ,  H01L21/027 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/3213

CPC分类号： G03F7/091 ,  G03F7/0045 ,  G03F7/0757 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S430/106 ,  Y10S430/115 ,  Y10S430/143 ,  Y10S430/151

摘要： Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.

摘要翻译： 提供了用于半导体器件加工的抗反射硬掩模组​​合物的抗反射硬掩模组​​合物和技术。 在本发明的一个方面，提供了用于光刻的抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。 在本发明的另一方面，提供一种用于处理半导体器件的方法。 该方法包括以下步骤：在衬底上提供材料层; 在材料层上形成抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。

公开(公告)号：US20070105363A1

公开(公告)日：2007-05-10

申请号：US11614799

申请日：2006-12-21

申请人： Katherina Babich ,  Elbert Huang ,  Arpan Mahorowala ,  David Medeiros ,  Dirk Pfeiffer ,  Karen Temple

发明人： Katherina Babich ,  Elbert Huang ,  Arpan Mahorowala ,  David Medeiros ,  Dirk Pfeiffer ,  Karen Temple

IPC分类号： H01L21/4763

CPC分类号： G03F7/091 ,  G03F7/0045 ,  G03F7/0757 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S430/106 ,  Y10S430/115 ,  Y10S430/143 ,  Y10S430/151

摘要： Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.

摘要翻译： 提供了用于半导体器件加工的抗反射硬掩模组​​合物的抗反射硬掩模组​​合物和技术。 在本发明的一个方面，提供了用于光刻的抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。 在本发明的另一方面，提供一种用于处理半导体器件的方法。 该方法包括以下步骤：在衬底上提供材料层; 在材料层上形成抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。

公开(公告)号：US20070015083A1

公开(公告)日：2007-01-18

申请号：US11180788

申请日：2005-07-14

申请人： Katherina Babich ,  Sean Burns ,  Elbert Huang ,  Arpan Mahorowala ,  Dirk Pfeiffer ,  Karen Temple

发明人： Katherina Babich ,  Sean Burns ,  Elbert Huang ,  Arpan Mahorowala ,  Dirk Pfeiffer ,  Karen Temple

IPC分类号： G03C1/00

CPC分类号： G03F7/091 ,  Y10T428/31663

摘要： An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1≦x≦2; 1≦y≦5; 1≧0; m>0; n>0; R is a chromophore, M is a metal selected from Group IIIB to Group VIB, lanthanides, Group IIIA, Group IVA except silicon; and L is an optional ligand. The invention is also directed to a process of making a lithographic structure including a silicon-metal oxide, antireflective material.

摘要翻译： 一种抗反射组合物和包含硅 - 金属氧化物，衍生自该组合物的抗反射材料的光刻结构。 抗反射组合物包含式I的聚合物，其中1≤x≤2; 1 <= y <= 5; 1> = 0; m> 0; n> 0; R是发色团，M是选自IIIB族至VIB族的镧系元素，镧系元素，IIIA族，IVA族除外; L是任选的配体。 本发明还涉及制备包括硅 - 金属氧化物，抗反射材料的光刻结构的方法。

公开(公告)号：US07648820B2

公开(公告)日：2010-01-19

申请号：US11614799

申请日：2006-12-21

申请人： Katherina Babich ,  Elbert Huang ,  Arpan P. Mahorowala ,  David R. Medeiros ,  Dirk Pfeiffer ,  Karen Temple

发明人： Katherina Babich ,  Elbert Huang ,  Arpan P. Mahorowala ,  David R. Medeiros ,  Dirk Pfeiffer ,  Karen Temple

IPC分类号： G03F7/20 ,  G03F7/30 ,  G03F7/36 ,  G03F7/09 ,  G03C1/825

CPC分类号： G03F7/091 ,  G03F7/0045 ,  G03F7/0757 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S430/106 ,  Y10S430/115 ,  Y10S430/143 ,  Y10S430/151

摘要： Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.

摘要翻译： 提供了用于半导体器件加工的抗反射硬掩模组​​合物的抗反射硬掩模组​​合物和技术。 在本发明的一个方面，提供了用于光刻的抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。 在本发明的另一方面，提供一种用于处理半导体器件的方法。 该方法包括以下步骤：在衬底上提供材料层; 在材料层上形成抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。

公开(公告)号：US07172849B2

公开(公告)日：2007-02-06

申请号：US10646307

申请日：2003-08-22

申请人： Katherina Babich ,  Elbert Huang ,  Arpan P. Mahorowala ,  David R. Medeiros ,  Dirk Pfeiffer ,  Karen Temple

发明人： Katherina Babich ,  Elbert Huang ,  Arpan P. Mahorowala ,  David R. Medeiros ,  Dirk Pfeiffer ,  Karen Temple

IPC分类号： G03C1/825 ,  G03C1/835 ,  G03F7/038 ,  G03F7/09

CPC分类号： G03F7/091 ,  G03F7/0045 ,  G03F7/0757 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S430/106 ,  Y10S430/115 ,  Y10S430/143 ,  Y10S430/151

摘要： Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.

摘要翻译： 提供了用于半导体器件加工的抗反射硬掩模组​​合物的抗反射硬掩模组​​合物和技术。 在本发明的一个方面，提供了用于光刻的抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。 在本发明的另一方面，提供一种用于处理半导体器件的方法。 该方法包括以下步骤：在衬底上提供材料层; 在材料层上形成抗反射硬掩模层。 抗反射硬掩模层包含含有至少一个生色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。

公开(公告)号：US20050087876A1

公开(公告)日：2005-04-28

申请号：US10627794

申请日：2003-07-25

申请人： Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

发明人： Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

IPC分类号： H01L20060101 ,  H01L21/00 ,  H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/02282 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

摘要： The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1≦v≦0.9, 0≦w≦0.5, 0.01≦x≦0.9, 0≦y≦0.7, 0.01≦z≦0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1

摘要翻译： 本发明包括一种互连结构，其中包括在其间形成的金属，层间电介质和陶瓷扩散阻挡层，其中陶瓷扩散阻挡层具有组成为N 其中0.1 <= v <= 0.9,0 <= w <= 0.5,0.01 <= x <= 0.9， 对于v + w + x + y + z = 1，0 <= y <= 0.7,0.01 <= z <= 0.8。 陶瓷扩散阻挡层用作金属的扩散阻挡层，即铜。 本发明还包括用于形成本发明的陶瓷扩散阻挡层的方法，该方法包括沉积具有组合物的组合物的聚合物预陶瓷的步骤 其中0.1

公开(公告)号：US20050206004A1

公开(公告)日：2005-09-22

申请号：US11128493

申请日：2005-05-13

申请人： Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

发明人： Stephan Cohen ,  Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

IPC分类号： H01L20060101 ,  H01L21/00 ,  H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/02282 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31663 ,  H01L2924/00

摘要： The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1≦v≦0.9, 0≦w≦0.5, 0.01≦x≦0.9, 0≦y≦0.7, 0.01≦z≦0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1

公开(公告)号：US20050008959A1

公开(公告)日：2005-01-13

申请号：US10915087

申请日：2004-08-10

申请人： Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

发明人： Stephen Gates ,  Jeffrey Hedrick ,  Elbert Huang ,  Dirk Pfeiffer

IPC分类号： G03G13/06 ,  H01L20060101 ,  H01L21/00 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/44 ,  H01L23/48 ,  H05B6/64

CPC分类号： H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/316 ,  Y10S430/146 ,  Y10T428/31663

摘要： The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNwCxOyHz where 0.1≦v≦0.9, 0≦w≦0.5, 0.05≦x≦0.9, 0≦y≦0.5, 0.05≦z≦0.8 for v+w+x+y+z=1; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNwCxOyHz where 0.05

摘要翻译： 本发明包括一种用于形成硬掩模的方法，包括以下步骤：在基底顶上沉积聚合物预陶瓷前体膜; 将聚合物前陶瓷前体膜转化为至少一个陶瓷层，其中陶瓷层具有SivNwCxOyHh的组成，其中0.1≤v≤0.9,0≤w≤0.5,0.05≤x≤0.9,0≤ 对于v + w + x + y + z = 1，y <= 0.5,0.05 <= z <= 0.8; 在陶瓷层顶部形成图案化的光刻胶; 图案化陶瓷层以暴露下面的衬底的区域，其中下面的衬底的剩余区域被图案化的陶瓷层保护; 并蚀刻下面的衬底的暴露区域。 本发明的另一方面是具有SivNwCxOyHz组成的掩埋蚀刻停止层，其中0.05≤v≤0.8,0

公开(公告)号：US20070111509A1

公开(公告)日：2007-05-17

申请号：US11619502

申请日：2007-01-03

申请人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

发明人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US20120187566A1

公开(公告)日：2012-07-26

申请号：US13013108

申请日：2011-01-25

申请人： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

摘要翻译： 公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。 该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件 离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。