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公开(公告)号：US07274625B1
公开(公告)日：2007-09-25
申请号：US11700876
申请日：2007-02-01
CPC分类号： G09G3/3611 , G09G3/20
摘要： An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control-electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j
摘要翻译： 振荡器电路包括当n为自然数时串联连接的（2n + 1）个反相器，具有连接到第（2n + 1）个反相器的输出端的输入端的积分器电路和连接到输入端的输出端 串联连接在第一反相器的输入端和第一参考电位之间的第一和第二p型晶体管，以及串联连接在第一反相器的输入端和第一反相器的第一和第二p型晶体管之间的第一和第二p型晶体管， 第二个参考电位。 将第j个反相器的输出电压施加到第一p型晶体管和第一n型晶体管的控制电极。 第k个反相器的输出电压被施加到第二p型晶体管和第二n型晶体管的控制电极。 符号j是奇数，k是偶数，并且满足j
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公开(公告)号：US20070182679A1
公开(公告)日：2007-08-09
申请号：US11700876
申请日：2007-02-01
IPC分类号： G09G3/34
CPC分类号： G09G3/3611 , G09G3/20
摘要： An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j
摘要翻译： 振荡器电路包括当n为自然数时串联连接的（2n + 1）个反相器，具有连接到第（2n + 1）个反相器的输出端的输入端的积分器电路和连接到输入端的输出端 串联连接在第一反相器的输入端和第一参考电位之间的第一和第二p型晶体管，以及串联连接在第一反相器的输入端和第一反相器的第一和第二p型晶体管之间的第一和第二p型晶体管， 第二个参考电位。 将第j个反相器的输出电压施加到第一p型晶体管和第一n型晶体管的控制电极。 第k个反相器的输出电压被施加到第二p型晶体管和第二n型晶体管的控制电极。 符号j是奇数，k是偶数，并且满足j
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公开(公告)号：US08456401B2
公开(公告)日：2013-06-04
申请号：US12222339
申请日：2008-08-07
申请人： Katsumi Matsumoto , Kozo Yasuda , Yasukazu Kimura , Takuo Kaitoh , Toshihiko Itoga , Hiroshi Kageyama
发明人： Katsumi Matsumoto , Kozo Yasuda , Yasukazu Kimura , Takuo Kaitoh , Toshihiko Itoga , Hiroshi Kageyama
IPC分类号： G09G3/36 , H01L31/00 , H01L31/036
CPC分类号： H01L29/78618 , G02F1/13454 , G02F2001/13685 , G02F2202/104 , H01L27/12 , H01L29/78645 , H01L29/78696
摘要： The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.
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公开(公告)号：US20090073149A1
公开(公告)日：2009-03-19
申请号：US12222339
申请日：2008-08-07
申请人： Katsumi Matsumoto , Kozo Yasuda , Yasukazu Kimura , Takuo Kaitoh , Toshihiko Itoga , Hiroshi Kageyama
发明人： Katsumi Matsumoto , Kozo Yasuda , Yasukazu Kimura , Takuo Kaitoh , Toshihiko Itoga , Hiroshi Kageyama
CPC分类号： H01L29/78618 , G02F1/13454 , G02F2001/13685 , G02F2202/104 , H01L27/12 , H01L29/78645 , H01L29/78696
摘要： The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.
摘要翻译： 栅电极通过栅极绝缘膜形成在多晶半导体层的上方。 多晶半导体层包括在平面图中与栅电极重叠的第一区域。 第一区域夹在第二区域和第三区域之间。 多晶半导体层的第二区域包括第一杂质扩散区域和与第一杂质扩散区域相反的导电类型的两个第二杂质扩散区域。 第一区域和第一杂质扩散区域在第一边界处彼此接触。 第一区域和第二第二杂质扩散区域在第二边界处彼此接触。 夹着第一杂质扩散区的两个第二杂质扩散区沿着栅电极设置。 因此，泄漏电流被抑制。
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公开(公告)号：US08102353B2
公开(公告)日：2012-01-24
申请号：US11902740
申请日：2007-09-25
申请人： Katsumi Matsumoto , Kozo Yasuda , Hiroshi Kageyama
发明人： Katsumi Matsumoto , Kozo Yasuda , Hiroshi Kageyama
IPC分类号： G09G3/36
CPC分类号： G09G3/3688
摘要： The present invention is to prevent a capture error of display data caused by a delay due to a built-in driving circuit in a display device with a built-in driving circuit. The display device comprises: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit that performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects the timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.
摘要翻译： 本发明是为了防止在具有内置驱动电路的显示装置中由于内置驱动电路引起的延迟引起的显示数据的捕获误差。 显示装置包括：具有多个子像素的显示区域; 以及形成在所述显示区域的周围的驱动电路; 其中所述驱动电路包括：第一扫描电路，其沿第一方向执行扫描; 以及锁存电路，其基于从所述第一扫描电路输出的扫描输出来锁存从外部输入的显示数据; 其中驱动电路包括一个定时校正电路，该定时校正电路根据从外部输入的显示数据同步时钟校正从第一扫描电路输出的扫描输出的电平变化的定时; 其中所述锁存电路通过从所述定时校正电路输出的经校正的扫描输出来锁存显示数据; 并且其中直到直到显示数据的锁存电路的传输线和直到显示数据同步时钟的定时校正电路的传输线相邻布置。
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公开(公告)号：US20080186291A1
公开(公告)日：2008-08-07
申请号：US11902740
申请日：2007-09-25
申请人： Katsumi Matsumoto , Kozo Yasuda , Hiroshi Kageyama
发明人： Katsumi Matsumoto , Kozo Yasuda , Hiroshi Kageyama
IPC分类号： G06F3/038
CPC分类号： G09G3/3688
摘要： The present invention is to prevent a capture error of display data caused by a delay due to a built-in driving circuit in a display device with a built-in driving circuit. The display device comprises: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit that performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects the timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.
摘要翻译： 本发明是为了防止在具有内置驱动电路的显示装置中由于内置驱动电路引起的延迟引起的显示数据的捕获误差。 显示装置包括：具有多个子像素的显示区域; 以及形成在所述显示区域的周围的驱动电路; 其中所述驱动电路包括：第一扫描电路，其沿第一方向执行扫描; 以及锁存电路，其基于从所述第一扫描电路输出的扫描输出来锁存从外部输入的显示数据; 其中驱动电路包括一个定时校正电路，该定时校正电路根据从外部输入的显示数据同步时钟校正从第一扫描电路输出的扫描输出的电平变化的定时; 其中所述锁存电路通过从所述定时校正电路输出的经校正的扫描输出来锁存显示数据; 并且其中直到直到显示数据的锁存电路的传输线和直到显示数据同步时钟的定时校正电路的传输线相邻布置。
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公开(公告)号：US07948461B2
公开(公告)日：2011-05-24
申请号：US11656428
申请日：2007-01-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G2300/0809 , G09G2300/0857 , G09G2310/0251 , G09G2330/021
摘要： The present invention provides an image display device having about the same numbers of gate lines and data lines as before and capable of reducing the power consumption of a static memory during rewriting of a display image. In the configuration of the image display device, the drain electrode of a first transistor 15 included in a pixel circuit is connected to an input for setting a storing state of the static memory, the drain electrode of a second transistor 18 is connected to an input for resetting a storing state of the static memory, the source electrode of the first transistor is connected to a data line, the gate electrode of the first transistor included in a row of pixel circuits arranged parallel to gate lines is connected to one gate line of the plurality of gate lines, and the gate electrode of the second transistor included in another row of pixel circuits arranged adjacent to the row of pixel circuits is connected to the one gate line.
摘要翻译： 本发明提供一种图像显示装置，其具有与之前相同数量的栅极线和数据线，并且能够在重写显示图像期间降低静态存储器的功耗。 在图像显示装置的结构中，包括在像素电路中的第一晶体管15的漏极连接到用于设置静态存储器的存储状态的输入端，第二晶体管18的漏电极连接到输入 为了重置静态存储器的存储状态，第一晶体管的源电极连接到数据线，包括在与栅极线平行布置的一行像素电路中的第一晶体管的栅电极连接到 多个栅极线以及与该像素电路行相邻配置的另一排像素电路中的第二晶体管的栅电极连接到一个栅极线。
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公开(公告)号：US20070176875A1
公开(公告)日：2007-08-02
申请号：US11656428
申请日：2007-01-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G2300/0809 , G09G2300/0857 , G09G2310/0251 , G09G2330/021
摘要： The present invention provides an image display device having about the same numbers of gate lines and data lines as before and capable of reducing the power consumption of a static memory during rewriting of a display image. In the configuration of the image display device, the drain electrode of a first transistor 15 included in a pixel circuit is connected to an input for setting a storing state of the static memory, the drain electrode of a second transistor 18 is connected to an input for resetting a storing state of the static memory, the source electrode of the first transistor is connected to a data line, the gate electrode of the first transistor included in a row of pixel circuits arranged parallel to gate lines is connected to one gate line of the plurality of gate lines, and the gate electrode of the second transistor included in another row of pixel circuits arranged adjacent to the row of pixel circuits is connected to the one gate line.
摘要翻译： 本发明提供一种图像显示装置，其具有与之前相同数量的栅极线和数据线，并且能够在重写显示图像期间降低静态存储器的功耗。 在图像显示装置的结构中，包括在像素电路中的第一晶体管15的漏极连接到用于设置静态存储器的存储状态的输入端，第二晶体管18的漏电极连接到输入 为了重置静态存储器的存储状态，第一晶体管的源电极连接到数据线，包括在与栅极线平行布置的一行像素电路中的第一晶体管的栅电极连接到 多个栅极线以及与该像素电路行相邻配置的另一排像素电路中的第二晶体管的栅电极连接到一个栅极线。
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公开(公告)号：US08013827B2
公开(公告)日：2011-09-06
申请号：US11806194
申请日：2007-05-30
CPC分类号： G09G3/3648 , G09G2300/0857 , G09G2310/0289 , G09G2310/08 , G09G2330/021
摘要： The present invention provides an image display device that is capable of reducing the power consumption. The total power consumption of a level shifter is reduced by using a pulse of an oscillator circuit as an enable signal of a level shifter for amplifying the enable signal to be supplied to a group of level shifters. The image display device includes an oscillator circuit, a first level shifter, and a plurality of second level shifters, which are mounted on a substrate and formed with thin-film transistors. The plurality of second level shifters each has a shutdown function for reducing the power consumption of the level shifters. The shutdown function of the first level shifter is controlled by an output pulse of the oscillator circuit. The shutdown function of the group of second level shifters is controlled by an output pulse of the first level shifter.
摘要翻译： 本发明提供能够降低功耗的图像显示装置。 通过使用振荡器电路的脉冲作为用于放大要提供给一组电平移位器的使能信号的电平移位器的使能信号来降低电平移位器的总功耗。 图像显示装置包括安装在基板上并形成有薄膜晶体管的振荡器电路，第一电平移位器和多个第二电平移位器。 多个第二电平移位器各自具有用于降低电平移位器的功耗的关断功能。 第一电平移位器的关断功能由振荡器电路的输出脉冲控制。 第二电平移位器组的关断功能由第一电平移位器的输出脉冲控制。
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公开(公告)号：US20070279366A1
公开(公告)日：2007-12-06
申请号：US11806194
申请日：2007-05-30
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2300/0857 , G09G2310/0289 , G09G2310/08 , G09G2330/021
摘要： The present invention provides an image display device that is capable of reducing the power consumption. The total power consumption of a level shifter is reduced by using a pulse of an oscillator circuit as an enable signal of a level shifter for amplifying the enable signal to be supplied to a group of level shifters. The image display device includes an oscillator circuit, a first level shifter, and a plurality of second level shifters, which are mounted on a substrate and formed with thin-film transistors. The plurality of second level shifters each has a shutdown function for reducing the power consumption of the level shifters. The shutdown function of the first level shifter is controlled by an output pulse of the oscillator circuit. The shutdown function of the group of second level shifters is controlled by an output pulse of the first level shifter.
摘要翻译： 本发明提供能够降低功耗的图像显示装置。 通过使用振荡器电路的脉冲作为用于放大要提供给一组电平移位器的使能信号的电平移位器的使能信号来降低电平移位器的总功耗。 图像显示装置包括安装在基板上并形成有薄膜晶体管的振荡器电路，第一电平移位器和多个第二电平移位器。 多个第二电平移位器各自具有用于降低电平移位器的功耗的关断功能。 第一电平移位器的关断功能由振荡器电路的输出脉冲控制。 第二电平移位器组的关断功能由第一电平移位器的输出脉冲控制。
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