公开(公告)号：US07737561B2

公开(公告)日：2010-06-15

申请号：US11968929

申请日：2008-01-03

申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔线路电平低k电介质层，其上具有金属线导体，其具有底部和侧壁; 在第一多孔线路低k电介质上的抛光停止层; 第二薄的无孔通孔级低k电介质层，用于涂覆和平坦化线和通孔侧壁; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：US07879717B2

公开(公告)日：2011-02-01

申请号：US12140854

申请日：2008-06-17

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/00

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料构成的掩埋蚀刻停止层，其中0.05和n1E; v和n1E; 0.8,0和n1E; w和n1E;0.9,0.05≤n1E; x和nlE; 0.8,0和nlE; y＆nlE; 0.3,0.05＆ 对于v + w + x + y + z = 1，z＆nlE; 0.8。 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07187081B2

公开(公告)日：2007-03-06

申请号：US10699238

申请日：2003-10-31

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L29/40

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US20080254612A1

公开(公告)日：2008-10-16

申请号：US12140854

申请日：2008-06-17

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, O≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8，O <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07396758B2

公开(公告)日：2008-07-08

申请号：US11619502

申请日：2007-01-03

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07338895B2

公开(公告)日：2008-03-04

申请号：US11341338

申请日：2006-01-26

申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

IPC分类号： H01L21/4763

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔低k线电介质层，其上具有底部和侧壁的金属线导体; 在第一多孔低k电介质上的抛光停止层; 用于涂覆和平坦化线和通孔侧壁的第二薄无孔低k介电层; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：US07057287B2

公开(公告)日：2006-06-06

申请号：US10645308

申请日：2003-08-21

申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔低k线电介质层，其上具有底部和侧壁的金属线导体; 在第一多孔低k电介质上的抛光停止层; 用于涂覆和平坦化线和通孔侧壁的第二薄无孔低k介电层; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：USRE45781E1

公开(公告)日：2015-10-27

申请号：US14176526

申请日：2014-02-10

申请人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

发明人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/70 ,  H01L23/52 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

公开(公告)号：US06783862B2

公开(公告)日：2004-08-31

申请号：US10290682

申请日：2002-11-08

申请人： Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

发明人： Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

IPC分类号： B32B904

CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

公开(公告)号：US08637412B2

公开(公告)日：2014-01-28

申请号：US13214157

申请日：2011-08-19

申请人： Alfred Grill ,  Thomas Jasper Haigh, Jr. ,  Kelly Malone ,  Son Van Nguyen ,  Vishnubhai Vitthalbhai Patel ,  Hosadurga Shobha

发明人： Alfred Grill ,  Thomas Jasper Haigh, Jr. ,  Kelly Malone ,  Son Van Nguyen ,  Vishnubhai Vitthalbhai Patel ,  Hosadurga Shobha

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/511 ,  C08J9/26 ,  C08J2201/042 ,  C08J2383/04 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L29/515 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first PECVD process incorporating a silicon oxide precursor alone and then with an organo-silicon precursor with increasing flow while the flow of the silicon oxide precursor is reduced to zero provides a graded carbon adhesion layer whereby the content of C increases with layer thickness and a second PECVD process incorporating an organo-silicon precursor including an organic porogen provides a multiphase ultra-low k dielectric. The multiphase ultra-low k PECVD process uses high frequency radio frequency power just above plasma initiation in a PECVD chamber. An energy post treatment is also provided. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is formed.

摘要翻译： 第一PECVD工艺，其单独掺入氧化硅前体，然后与有机硅前驱物同时增加流动，同时氧化硅前体的流动减少至零，从而提供渐变的碳粘附层，由此C的含量随层的厚度而增加， 结合包含有机致孔剂的有机硅前体的第二PECVD工艺提供了多相超低k电介质。 多相超低k PECVD工艺在PECVD室中使用高于等离子体起始的高频射频功率。 还提供了能量后处理。 形成k小于2.7且弹性模量大于7GPa的多孔SiCOH电介质材料。