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    INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY
    4.
    发明申请
    INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY 有权
    具有增强可靠性的互连结构

    公开(公告)号：US20120104610A1

    公开(公告)日：2012-05-03

    申请号：US12915510

    申请日：2010-10-29

    申请人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

    发明人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

    摘要翻译： 一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。 还提供了形成互连结构的方法。

    METHOD FOR VIA PLATING IN ELECTRONIC PACKAGES CONTAINING FLUOROPOLYMER DIELECTRIC LAYERS
    6.
    发明申请
    METHOD FOR VIA PLATING IN ELECTRONIC PACKAGES CONTAINING FLUOROPOLYMER DIELECTRIC LAYERS 审中-公开
    用于在含有荧光体介质层的电子封装中进行镀覆的方法

    公开(公告)号：US20110260299A1

    公开(公告)日：2011-10-27

    申请号：US12765110

    申请日：2010-04-22

    申请人： Robert D. Edwards ,  Frank D. Egitto ,  Luis J. Matienzo ,  Susan Pitely ,  Daniel C. Van Hart

    发明人： Robert D. Edwards ,  Frank D. Egitto ,  Luis J. Matienzo ,  Susan Pitely ,  Daniel C. Van Hart

    IPC分类号： H01L23/50 ,  H05K3/00 ,  H01L21/441

    CPC分类号： H05K3/0055 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K2201/015 ,  H05K2201/09509 ,  H05K2203/095 ,  H01L2924/00

    摘要： A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA.

    摘要翻译： 一种半导体印刷电路板组件（PCBA）及其制造方法，用于具有放置在芯层上的介电基片层的具有铜 - 铜 - 铜（CIC）芯层的电子封装。 第二层电介质基片放置在CIC芯层的下表面上。 层叠在一起。 盲孔通过激光钻入电介质基片的层中。 部分完成的PCBA经受反应离子蚀刻（RIE）等离子体作为清洁PCBA中的盲孔的第一步骤。 在等离子体蚀刻之后，在盲孔上使用酸性蚀刻剂液体溶液。 盲孔的电镀前清洁从盲孔中除去大部分氧化物。 然后将种子铜层施加到PCBA，随后是可以被蚀刻以满足PCBA的要求的一层镀铜层。

    Process of enclosing via for improved reliability in dual damascene interconnects
    7.
    发明授权
    Process of enclosing via for improved reliability in dual damascene interconnects 有权
    封装通孔的过程可提高双镶嵌互连中的可靠性

    公开(公告)号：US06383920B1

    公开(公告)日：2002-05-07

    申请号：US09757894

    申请日：2001-01-10

    申请人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

    发明人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

    IPC分类号： H01L214763

    CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

    摘要翻译： 本发明一般涉及在双镶嵌工艺中封闭通孔的方法。 在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽 在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。 或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在 双镶嵌工艺。 阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。