公开(公告)号：US07473636B2

公开(公告)日：2009-01-06

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US08465657B2

公开(公告)日：2013-06-18

申请号：US11833283

申请日：2007-08-03

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewara ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewara ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US07820559B2

公开(公告)日：2010-10-26

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/31 ,  H01L21/4763

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘附过渡层包括下部含SiO x或SiON的区域和上部C分级区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20080254643A1

公开(公告)日：2008-10-16

申请号：US12143917

申请日：2008-06-23

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Darren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07402532B2

公开(公告)日：2008-07-22

申请号：US11499220

申请日：2006-08-04

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US07102232B2

公开(公告)日：2006-09-05

申请号：US10827693

申请日：2004-04-19

申请人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Stefanie R. Chiras ,  Timothy Dalton ,  James J. Demarest ,  Derren N. Dunn ,  Chester T. Dziobkowski ,  Philip L. Flaitz ,  Michael W. Lane ,  James R. Lloyd ,  Darryl D. Restaino ,  Thomas M. Shaw ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。

公开(公告)号：US20130017680A1

公开(公告)日：2013-01-17

申请号：US13182544

申请日：2011-07-14

申请人： Balasubramanian S. Haran ,  James J. Demarest

发明人： Balasubramanian S. Haran ,  James J. Demarest

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/7833

摘要： A method of making a gate of a field effect transistor (FET) with improved fill by a replacement gate process using a sacrificial film includes providing a substrate with a dummy gate. It further includes depositing a sacrificial layer and an encapsulating layer over the substrate, and planarizing so that the encapsulating layer, sacrificial layer and dummy gate are co-planar. The encapsulating layer and a portion of the sacrificial film are removed to leave a remaining sacrificial film. The dummy gate is removed to form and opening in the remaining sacrificial film and to expose sidewalls of the film. Spacers are formed on the sidewalls. A high dielectric constant film and metal film are deposited in the opening and planarized to form a gate. The remaining sacrificial film is removed. The method can be used on planar FETs as well non-planar FETs.

摘要翻译： 通过使用牺牲膜的替换栅极处理来改善填充的场效应晶体管（FET）的栅极的方法包括向衬底提供虚拟栅极。 其还包括在衬底上沉积牺牲层和封装层，并且平坦化，使得封装层，牺牲层和伪栅极是共面的。 去除封装层和牺牲膜的一部分以留下剩余的牺牲膜。 去除虚拟栅极以在剩余的牺牲膜中形成和打开并暴露膜的侧壁。 隔板形成在侧壁上。 将高介电常数的膜和金属膜沉积在开口中并平坦化以形成栅极。 剩余的牺牲膜被去除。 该方法可用于平面FET以及非平面FET。

公开(公告)号：US20080270081A1

公开(公告)日：2008-10-30

申请号：US11742095

申请日：2007-04-30

申请人： Delia R. Bearup ,  Andrew S. Dalton ,  James J. Demarest ,  Loren L. Hahn ,  Bruce J. Redder ,  Francis R. Wallingford

发明人： Delia R. Bearup ,  Andrew S. Dalton ,  James J. Demarest ,  Loren L. Hahn ,  Bruce J. Redder ,  Francis R. Wallingford

IPC分类号： G06F15/00

CPC分类号： G01R31/307 ,  H01J37/268 ,  H01J2237/24475 ,  H01J2237/2448 ,  H01J2237/24495 ,  H01J2237/24564 ,  H01J2237/2594

摘要： Non-destructive, below-surface defect rendering of an IC chip using image intensity analysis is disclosed. One method includes providing an IC chip delayered to a selected layer; determining a defect location below a surface of the selected layer using a first image of the IC chip obtained using an CPIT in a first mode; generating a second image of the IC chip with the CPIT in a second mode, the second image representing charged particle signal from the defect below the surface of the selected layer; and rendering the defect by comparing an image intensity of a reference portion of the second image not including the defect with the image intensity of a defective portion of the second image including the defect, wherein the reference portion and the defective portion are of structures expected to be substantially identical.

摘要翻译： 公开了使用图像强度分析的IC芯片的非破坏性的表面下缺陷渲染。 一种方法包括提供延迟到选定层的IC芯片; 使用在第一模式中使用CPIT获得的IC芯片的第一图像来确定所选层的表面下方的缺陷位置; 在第二模式中用CPIT生成IC芯片的第二图像，第二图像表示来自所选层的表面下方的缺陷的带电粒子信号; 并且通过将不包括缺陷的第二图像的参考部分的图像强度与包括缺陷的第二图像的缺陷部分的图像强度进行比较来呈现缺陷，其中参考部分和缺陷部分具有预期的结构 基本相同。

公开(公告)号：US08889564B2

公开(公告)日：2014-11-18

申请号：US13600324

申请日：2012-08-31

申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。