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    Interconnect structure for integrated circuits having improved electromigration characteristics
    1.
    发明授权
    Interconnect structure for integrated circuits having improved electromigration characteristics 有权
    具有改进的电迁移特性的集成电路的互连结构

    公开(公告)号：US08056039B2

    公开(公告)日：2011-11-08

    申请号：US12128973

    申请日：2008-05-29

    申请人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    发明人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    IPC分类号： G06F17/50

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

    摘要翻译： 用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。 。 。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。 。 。 选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保​​持为 导线的总长度L = L1 + L2 +。 。 。 + LN，无论临界长度如何，满足最小设计长度。

    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS
    4.
    发明申请
    INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS 有权
    具有改善电磁特性的集成电路的互连结构

    公开(公告)号：US20090294973A1

    公开(公告)日：2009-12-03

    申请号：US12128973

    申请日：2008-05-29

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

    IPC分类号： H01L23/538 ,  H01L21/768

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

    摘要翻译： 用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。 。 。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。 。 。 选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保​​持为 导线的总长度L = L1 + L2 +。 。 。 + LN，无论临界长度如何，满足最小设计长度。

    Reliability of wide interconnects
    9.
    发明授权
    Reliability of wide interconnects 失效
    宽互连的可靠性

    公开(公告)号：US07776737B2

    公开(公告)日：2010-08-17

    申请号：US12191534

    申请日：2008-08-14

    申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

    摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。