摘要:
A semiconductor chip is provided with a function selection circuit for selecting memory functions according to the information stored in nonvolatile memory elements is sealed in a package, and the memory functions are set finally by writing the nonvolatile memory element in that state or in a state in which the semiconductor chip is mounted on a board. By setting the type of a semiconductor memory according to the above procedure, the process from the wafer process up to the assembling step can be made common, and hence the mass-productibity and the production control can be facilitated. Semiconductor memories having memory functions conforming to user specifications can be provided in a short time.
摘要:
A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.
摘要:
It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要:
A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.