公开(公告)号：US4920546A

公开(公告)日：1990-04-24

申请号：US176294

申请日：1988-03-31

申请人： Kazuo Iguchi ,  Tetsuo Soejima ,  Kazuo Murano ,  Shigeo Amemiya ,  Hiroaki Komine ,  Toshiaki Watanabe ,  Tomohiro Shinomiya

发明人： Kazuo Iguchi ,  Tetsuo Soejima ,  Kazuo Murano ,  Shigeo Amemiya ,  Hiroaki Komine ,  Toshiaki Watanabe ,  Tomohiro Shinomiya

IPC分类号： H04J3/06

CPC分类号： H04J3/0605

摘要： Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.

公开(公告)号：US4924461A

公开(公告)日：1990-05-08

申请号：US286872

申请日：1988-12-20

申请人： Shigeo Amemiya ,  Hiroaki Komine ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

发明人： Shigeo Amemiya ,  Hiroaki Komine ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

IPC分类号： H04L12/403

CPC分类号： H04L12/403

摘要： In a sequential polling type communication network system including a master station, a first channel, a second channel, and at least two slave stations, the master station includes request registration units for registering data transmission requests from slave stations during a data transmission by another slave station, and an interrupt polling unit for polling the slave station which has issued the data transmission request after completion of the data transmission or completion of a polling of a slave station, and the slave station includes a unit for responding to a polling during the data transmission, and transitting a data transmission request when data to be transmitted exists, and for responding to the interrupt polling from the master station, and transmitting the data to the master station until the data transmission is completed.

公开(公告)号：US5132680A

公开(公告)日：1992-07-21

申请号：US447432

申请日：1989-12-07

申请人： Koji Tezuka ,  Tomohiro Shinomiya ,  Shigeo Amemiya ,  Kazuo Iguchi ,  Tetsuo Soejima

发明人： Koji Tezuka ,  Tomohiro Shinomiya ,  Shigeo Amemiya ,  Kazuo Iguchi ,  Tetsuo Soejima

IPC分类号： H04L12/403

CPC分类号： H04L12/403

摘要： A communication system including a master station, a plurality of slave stations each for communicating with the master station, a two-way transmission line connecting the master station and the plurality of slave stations. Each of the slave stations sends a request for further communication with the master station, to the master station when its own slave station is allowed to communicate with the master station and its own slave station has the above request. The master station detects the request for further communication with the master station in a signal sent from a slave station, and memorizes the slave station from which the request for further communication with the master station is detected, until an allowance signal is sent to the slave station from the master station corresponding to the memorizing of the slave station. The master station has a cyclic address pointer which points to an address of a next one of the slave stations in a cyclic order when no slave station is memorized in the master station. The master station outputs the allowance signal to communicate with the master station to a slave station which is memorized in the master station or to a slave station the address of which is pointed to by the cyclic address pointer when no request is memorized in the master station.

公开(公告)号：US4850047A

公开(公告)日：1989-07-18

申请号：US86807

申请日：1987-08-19

申请人： Kazuo Iguchi ,  Tetsuo Soejima ,  Shigeo Amemiya ,  Hiroaki Komine

发明人： Kazuo Iguchi ,  Tetsuo Soejima ,  Shigeo Amemiya ,  Hiroaki Komine

IPC分类号： H04B10/213 ,  H04J14/08 ,  H04L12/28 ,  H04Q11/04

CPC分类号： H04Q11/0428 ,  H04J14/08 ,  H04L12/28 ,  H04J14/083

摘要： An optical bus type communication system comprises a bus type transmission line consisting of an optical fiber, a light source provided at the one end of the bus type transmission line for sending an optical signal having a constant level to the bus type transmission line, a plurality of optical switches mounted on the bus type transmission line, and a plurality of terminal interfaces. Each terminal interface sends data by switching the corresponding optical switch so that the optical signals on the transmission line are modulated with the data.

摘要翻译： 一种光总线型通信系统，包括由光纤组成的总线型传输线，设置在总线型传输线一端的光源，用于向总线型传输线发送具有恒定电平的光信号，多个 安装在总线型传输线上的光开关，以及多个端子接口。 每个终端接口通过切换相应的光开关发送数据，使得传输线上的光信号被数据调制。

公开(公告)号：US5166675A

公开(公告)日：1992-11-24

申请号：US726637

申请日：1991-07-02

申请人： Shigeo Amemiya ,  Koji Tezuka ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Tetsuo Soejima ,  Kazuo Iguchi

发明人： Shigeo Amemiya ,  Koji Tezuka ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Tetsuo Soejima ,  Kazuo Iguchi

IPC分类号： H04L12/403

CPC分类号： H04L12/40143 ,  H04L12/403

摘要： A communication system containing a master station and a plurality of slave stations. The master station receives a request from one of the plurality of slave stations and memorizes one or more requests from one or more slave stations. The master station also sends a request sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send a request for sending data, and sends a data sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send data, according to a request which is memorized. Each of the slave stations detects a request sending allowance signal which addresses its own slave station, and a data sending allowance signal which addresses its own slave station. Each of the slave stations also sends a request for sending data to the master station when its own slave station detects a request sending allowance signal which addresses its own slave station. In addition, each slave station sends data to the master station when its own slave station detects a data sending allowance signal which addresses its own slave station.

摘要翻译： 一种包含主站和多个从站的通信系统。 主站接收来自多个从站中的一个的请求，并存储来自一个或多个从站的一个或多个请求。 主站还发送请求发送允许信号，该请求发送允许信号寻址多个从站中的一个从站给发送请求发送数据的余地，并且发送寻址多个从站中的一个从站的数据发送允许信号，以给出 根据要记录的要求发送数据。 每个从站检测到寻址其自己的从站的请求发送允许信号，以及寻址其自己的从站的数据发送允许信号。 当其自己的从站检测到寻址其自己的从站的请求发送允许信号时，每个从站还发送向主站发送数据的请求。 另外，每个从站在其自己的从站检测到寻址其自己的从站的数据发送允许信号时，向主站发送数据。

公开(公告)号：US5086436A

公开(公告)日：1992-02-04

申请号：US529326

申请日：1990-05-29

申请人： Koji Tezuka ,  Shigeo Amemiya ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

发明人： Koji Tezuka ,  Shigeo Amemiya ,  Tomohiro Shinomiya ,  Kazuo Iguchi ,  Tetsuo Soejima

IPC分类号： H04L25/38 ,  H03M7/30 ,  H04L7/04 ,  H04L25/49

CPC分类号： H04L25/491 ,  H03M7/30

摘要： A coded transmission system wherein each bit of transmitted data having a logical value is coded depending on a coded result of a preceding bit. The coded transmission system contains a sender-side apparatus, a transmission line, and a receiver-side apparatus. In the sender-side apparatus, a resetting bit and a message are generated; a code of a bit last transmitted which is necessary to code a bit which is to be transmitted next is memorized in a first preceding code memorizing circuit; and the content of the first preceding code memorizing circuit is reset to an initial code responding to the resetting bit. A coding circuit receives the resetting bit and the message, codes each bit of the message in accordance with a predetermined coding rule and the content of the first preceding code memorizing circuit, and codes the resetting bit to a predetermined resetting code which is different from the codes used in the coding of the message. In the receiver-side apparatus, a code of a bit last received which is necessary to decode a code of a bit which is received next is memorized in a second preceding code memorizing circuit. A resetting circuit resets a content of a second preceding code memorizing circuit to a predetermined initial code when receiving the resetting code. A decoding circuit decodes the received codes corresponding to the message in accordance with the predetermined coding rule and the content of the second preceding code memorizing circuit.

公开(公告)号：US4977558A

公开(公告)日：1990-12-11

申请号：US485833

申请日：1990-02-28

申请人： Kazuo Iguchi ,  Tetsuo Soejima ,  Toshiaki Watanabe ,  Shigeo Amemiya

发明人： Kazuo Iguchi ,  Tetsuo Soejima ,  Toshiaki Watanabe ,  Shigeo Amemiya

IPC分类号： H04J3/06

CPC分类号： H04J3/0602

摘要： A circuit which operates at the fixed timing and discriminates the control signal is provided and the timing pulse for demultiplexing is controlled in accordance with the discriminated control signal in the receiving part of the synchronized multiplexing system in which the basic signals are generated by inserting the control signal required for multiplexing on the frame structure of basic signal rate and the high level multiplexing signal is formed by multiplexing such basic signals, thereby stable correspondence between the channel at the time of multiplexing in the sending side and the channel after the demultiplexing in the receiving side can be ensured.

公开(公告)号：US4984238A

公开(公告)日：1991-01-08

申请号：US320588

申请日：1989-03-08

申请人： Toshiaki Watanabe ,  Kazuo Iguchi ,  Tetsuo Soejima

发明人： Toshiaki Watanabe ,  Kazuo Iguchi ,  Tetsuo Soejima

IPC分类号： H04J3/06 ,  H04L7/08

CPC分类号： H04J3/0605 ,  H04L7/08

摘要： A frame synchronization method in which a synchronization detection of a frame synchronization signal using one of n-multiplexed frame synchronization signals derived from a sequence of frame synchronization signals each delayed by one bit from the preceding frame synchronization signal, a synchronization confirmation as synchronization guard by detecting a repetition of the synchronization detections of the frame synchronization signal, a confirmation of the subsequent frame identification signal based on the synchronization confirmation; and a separation of the received multiplexed signals into a plurality of channels based on the synchronization confirmed frame synchronization signal and the confirmed frame identification signal are carried out.

公开(公告)号：US4920535A

公开(公告)日：1990-04-24

申请号：US284395

申请日：1988-12-14

申请人： Toshiaki Watanabe ,  Kazuo Iguchi ,  Tetsuo Soejima ,  Shinji Ohta

发明人： Toshiaki Watanabe ,  Kazuo Iguchi ,  Tetsuo Soejima ,  Shinji Ohta

IPC分类号： H04J3/04 ,  H04J3/06 ,  H04L7/08

CPC分类号： H04J3/0602 ,  H04J3/047

摘要： A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.

公开(公告)号：US5475383A

公开(公告)日：1995-12-12

申请号：US849670

申请日：1992-03-11

申请人： Shinji Ohta ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Misao Fukuda ,  Kazuo Iguchi

发明人： Shinji Ohta ,  Tomohiro Shinomiya ,  Hiroshi Takeo ,  Misao Fukuda ,  Kazuo Iguchi

IPC分类号： H04Q3/52 ,  H04L12/931 ,  H04Q1/00

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/1576 ,  H04L49/255 ,  H04L2012/5681

摘要： A cross-point type switch includes a plurality of basic elements arranged in rows and columns so as to form a matrix arrangement of the basic elements. Each of the basic elements includes a plurality of input ports, output ports, expanded input ports and expanded output ports. A write/read part is connected to a common memory and has the function of writing data into the common memory and reading out the data from the common memory. A selector part selectively outputs either the data read out from the common memory or data from the expanded input ports to the output ports. The expanded output ports are directly connected to the input ports.

摘要翻译： 交叉点型开关包括以行和列布置的多个基本元件，以形成基本元件的矩阵排列。 每个基本元件包括多个输入端口，输出端口，扩展输入端口和扩展输出端口。 写/读部分连接到公共存储器，并且具有将数据写入公共存储器并从公共存储器读出数据的功能。 选择器部分选择性地将从公共存储器读出的数据或从扩展的输入端口的数据输出到输出端口。 扩展的输出端口直接连接到输入端口。