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    Method of testing analog/digital converter and structure of analog/digital converter suited for the test
    1.
    发明授权
    Method of testing analog/digital converter and structure of analog/digital converter suited for the test 失效
    测试模拟/数字转换器和模拟/数字转换器结构的测试方法

    公开(公告)号：US4580126A

    公开(公告)日：1986-04-01

    申请号：US669349

    申请日：1984-11-08

    申请人： Kazuo Kato ,  Takeshi Hirayama ,  Shigeaki Yoshida ,  Yoshinori Sato

    发明人： Kazuo Kato ,  Takeshi Hirayama ,  Shigeaki Yoshida ,  Yoshinori Sato

    IPC分类号： G01R31/00 ,  G01D21/00 ,  H03M1/00 ,  H03M1/10 ,  H03M1/48 ,  H03K13/09

    CPC分类号： H03M1/109 ,  H03M1/1047

    摘要： A method of testing a successive comparison type analog/digital converter which incorporates a voltage comparator, a register for successive comparison and a digital/analog converter. A reference digital signal is inputted to the incorporated digital/analog comparator to be converted into an analog signal, while a digital signal corresponding to the reference digital signal is inputted to an externally provided reference digital/analog converter to be converted into an analog signal. Both analog signals thus produced are compared with each other through the incorporated voltage comparator to thereby determine conversion accuracy. A successive comparison type analog/digital converter suited for the test includes further a change-over switch for introducing the externally supplied digital signal to the incorporated digital/analog converter and a changeover switch for leading outwardly the output signal from the voltage comparator.

    摘要翻译： 一种测试连续比较型模拟/数字转换器的方法，其包括电压比较器，用于连续比较的寄存器和数字/模拟转换器。 参考数字信号被输入到并入的数字/模拟比较器，以转换为模拟信号，而与参考数字信号相对应的数字信号被输入到外部提供的参考数字/模拟转换器，以转换为模拟信号。 通过并入的电压比较器将由此产生的两个模拟信号彼此进行比较，从而确定转换精度。 适用于测试的连续比较型模/数转换器还包括用于将外部提供的数字信号引入到并入的数字/模拟转换器的转换开关和用于向外引导来自电压比较器的输出信号的转换开关。

    Chronograph timepiece
    5.
    发明申请
    Chronograph timepiece 有权
    计时钟表

    公开(公告)号：US20110122734A1

    公开(公告)日：2011-05-26

    申请号：US12927305

    申请日：2010-11-10

    申请人： Kazuo Kato ,  Akira Takakura ,  Kenji Ogasawara ,  Saburo Manaka ,  Kazumi Sakumoto ,  Hiroshi Shimizu ,  Tomohiro Ihashi ,  Keishi Honmura ,  Takanori Hasegawa ,  Kosuke Yamamoto ,  Eriko Noguchi

    发明人： Kazuo Kato ,  Akira Takakura ,  Kenji Ogasawara ,  Saburo Manaka ,  Kazumi Sakumoto ,  Hiroshi Shimizu ,  Tomohiro Ihashi ,  Keishi Honmura ,  Takanori Hasegawa ,  Kosuke Yamamoto ,  Eriko Noguchi

    IPC分类号： G04F8/00

    CPC分类号： G04F7/0804

    摘要： Disclosed is a chronograph timepiece whose chronograph hands are electrically drive-controlled and mechanically zero-restoring-controlled, wherein it possible to perform a normal operation at the time of start operation and reset operation. After a mechanical control unit releases the setting of chronograph hands in response to the start operation of a start/stop button, a contact portion is placed in a start state, and an electrical control unit starts a time measurement operation to electrically hand-movement-drive the chronograph hands, and, after a contact portion is placed in a reset state in response to a reset operation of a reset button and the electrical control unit electrically resets the time measurement operation, the mechanical control unit mechanically zero-restores and sets the chronograph hands.

    摘要翻译： 本发明公开了一种计时手表，其计时指针由电驱动控制和机械零恢复控制，其中可以在开始操作和复位操作时执行正常操作。 在机械控制单元响应于启动/停止按钮的开始操作来释放计时指针的设置之后，将接触部分置于开始状态，并且电气控制单元开始时间测量操作以电动手动移动， 驱动计时指针，并且在响应于复位按钮的复位操作而将接触部分置于复位状态之后，电气控制单元电气地重置时间测量操作时，机械控制单元机械地恢复并设置 计时手

    Stepping motor control circuit and analog electronic watch
    7.
    发明申请
    Stepping motor control circuit and analog electronic watch 失效
    步进电机控制电路和模拟电子手表

    公开(公告)号：US20100238767A1

    公开(公告)日：2010-09-23

    申请号：US12661359

    申请日：2010-03-16

    申请人： Keishi Honmura ,  Saburo Manaka ,  Kosuke Yamamoto ,  Akira Takakura ,  Kenji Ogasawara ,  Kazumi Sakumoto ,  Kazuo Kato ,  Takanori Hasegawa

    发明人： Keishi Honmura ,  Saburo Manaka ,  Kosuke Yamamoto ,  Akira Takakura ,  Kenji Ogasawara ,  Kazumi Sakumoto ,  Kazuo Kato ,  Takanori Hasegawa

    IPC分类号： G04B19/04 ,  H02P8/38

    CPC分类号： G04C3/143 ,  H02P8/02

    摘要： A stepping motor control circuit includes a rotation detecting means which detects an induced signal generated by rotation of a rotor of a stepping motor, and detects a rotation state of the stepping motor according to whether the induced signal exceeds a predetermined reference threshold voltage in a predetermined detection section, and a control means which controls driving of the stepping motor by using any one of a plurality of main driving pulses having energies different from each other or a correction driving pulse with energy higher than energy of each main driving pulse according to a detection result of the rotation detecting means. The detection section is divided into a first section immediately after driving by the main driving pulse, a second section after the first section and a third section after the second section. During the driving of the stepping motor by the main driving pulse, when the rotation detecting means has detected an induced signal exceeding a first reference threshold voltage in the first section and the second section, if an induced signal exceeding a second reference threshold voltage lower than the first reference threshold voltage is not detected in the third section, the control means drives the stepping motor by using the correction driving pulse.

    摘要翻译： 步进电动机控制电路包括旋转检测装置，其检测由步进电动机的转子旋转产生的感应信号，并且根据感应信号是否超过预定的参考阈值电压来检测步进电动机的旋转状态 检测部分和控制装置，其通过使用具有彼此不同的能量的多个主驱动脉冲中的任何一个来控制步进电机的驱动，或者根据检测来控制具有高于每个主驱动脉冲的能量的能量的校正驱动脉冲 旋转检测装置的结果。 检测部分通过主驱动脉冲被分成紧接在驱动之后的第一部分，第一部分之后的第二部分和第二部分之后的第三部分。 在通过主驱动脉冲驱动步进电机的过程中，当旋转检测装置在第一部分和第二部分检测到超过第一参考阈值电压的感应信号时，如果超过第二参考阈值电压的感应信号低于 在第三部分中没有检测到第一参考阈值电压，控制装置通过使用校正驱动脉冲来驱动步进电机。

    Semiconductor integrated circuit having test function and manufacturing method
    9.
    发明申请
    Semiconductor integrated circuit having test function and manufacturing method 审中-公开
    具有测试功能和制造方法的半导体集成电路

    公开(公告)号：US20060184848A1

    公开(公告)日：2006-08-17

    申请号：US11335606

    申请日：2006-01-20

    申请人： Mitsuo Serizawa ,  Kaname Yamasaki ,  Masafumi Yamamoto ,  Kazuo Kato

    发明人： Mitsuo Serizawa ,  Kaname Yamasaki ,  Masafumi Yamamoto ,  Kazuo Kato

    IPC分类号： G01R31/28

    CPC分类号： G11C29/4401 ,  G01R31/318569 ,  G11C29/44 ,  G11C29/848 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/3202

    摘要： The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching signals between said logic circuit and said memory circuit and also forming a shift register. Moreover, the logic integrated circuit is further provided with a fail relief information generating circuit for storing test result to the boundary latch circuit during execution of the test with the test circuit and generating the fail relief information for relieving fail of said memory circuit based on the stored test result. The test circuit mounted on the logic integrated circuit can generate the information for relieving fail bit in parallel with the test of a built-in memory circuit and can also output the same information to external side and relieve the RAM within a chip.

    摘要翻译： 逻辑集成电路包括具有预定逻辑功能的逻辑电路，读/写存储器电路，用于测试故障位是否包含在存储器电路中的测试电路，以及由多个触发器组成的边界锁存电路， 触发电路，其能够在所述逻辑电路和所述存储器电路之间锁存信号，并且还形成移位寄存器。 此外，逻辑集成电路还设置有故障补救信息生成电路，用于在与测试电路执行测试期间将测试结果存储到边界锁存电路，并且基于该测试电路产生用于缓解所述存储器电路的故障的故障排除信息 存储测试结果。 安装在逻辑集成电路上的测试电路可以生成与内置存储器电路的测试并行的解除故障位的信息，并且还可以向外部输出相同的信息并释放芯片内的RAM。

    Phase-locked loop circuit, information processing apparatus, and information processing system
    10.
    发明授权
    Phase-locked loop circuit, information processing apparatus, and information processing system 失效
    锁相环电路，信息处理装置和信息处理系统

    公开(公告)号：US06947514B1

    公开(公告)日：2005-09-20

    申请号：US09446507

    申请日：1998-06-26

    申请人： Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Hirokazu Aoki ,  Kozaburo Kurita

    发明人： Kazuo Kato ,  Takashi Sase ,  Takashi Hotta ,  Hirokazu Aoki ,  Kozaburo Kurita

    IPC分类号： H03L7/113 ,  H03D3/24 ,  H03L7/06

    CPC分类号： H03L7/113

    摘要： A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

    摘要翻译： 提供锁相环（PLL）电路以在宽带中操作，包括两个单独的环路，其中一个用于通过其关联比例控制单元将振荡器的输出反馈到同一个振荡器，而另一个 用于通过集成控制单元将振荡器的输出反馈到同一个振荡器。 比例控制单元被布置成控制振荡器的输出频率，并且可操作以基于输入和输出信号之间的差产生控制信号。 积分控制单元被布置成控制振荡器的输出信号的相位，从而基于输入和输出信号之间的相位差产生控制信号。