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公开(公告)号：US5119062A
公开(公告)日：1992-06-02
申请号：US615369
申请日：1990-11-19
申请人： Kazutaka Nakamura , Hiroaki Taira , Tohru Higashi , Akinori Nakayama , Yasunobu Yoneda , Yukio Sakabe
发明人： Kazutaka Nakamura , Hiroaki Taira , Tohru Higashi , Akinori Nakayama , Yasunobu Yoneda , Yukio Sakabe
IPC分类号： H01C7/10
CPC分类号： H01C7/10
摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.
摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。
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公开(公告)号：US07415318B2
公开(公告)日：2008-08-19
申请号：US11244166
申请日：2005-10-06
申请人： Tohru Higashi
发明人： Tohru Higashi
IPC分类号： G06F19/00 , H01L21/8283
CPC分类号： G03F7/70633
摘要： Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
摘要翻译： 关于组成一批的多个晶片，预先测量这些晶片的对准标记和转印在光致抗蚀剂上的取向图案之间的未对准量，然后，层间电介质膜的厚度和晶片尺寸的值之间的相互关系 被计算。 当实际执行曝光时，首先，在对准标记上大量地形成层间电介质膜并进行平面化。 之后，测定平坦化后的层间电介质膜的厚度。 晶片缩放的值根据批次中的层间电介质膜的厚度的平均值和上述相互关系来估计。 然后，将光致抗蚀剂涂布在批次中的层间电介质膜上，并且在执行校正的同时曝光光致抗蚀剂以补偿晶片缩放的值。
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公开(公告)号：US07651826B2
公开(公告)日：2010-01-26
申请号：US11291318
申请日：2005-11-30
申请人： Mika Takahara , Tohru Higashi , Shigehiro Toyoda
发明人： Mika Takahara , Tohru Higashi , Shigehiro Toyoda
CPC分类号： G03F7/70641 , G03F1/44
摘要： There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern having at least one pair of first and second patterns, and the first pattern has an unexposed region surrounded by an exposed region, and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer, the first pattern having an unexposed region surrounded by an exposed region, the second pattern having an exposed region surrounded by an unexposed region, and checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.
摘要翻译： 提供了一种包括晶片和形成在晶片上的聚焦监视图案的半导体器件。 具有至少一对第一和第二图案的焦点监视图案，并且第一图案具有由曝光区域包围的未曝光区域，并且第二图案具有被未曝光区域包围的曝光区域。 另外，本发明提供一种制造半导体器件的方法，包括以下步骤：在晶片上形成至少一对第一和第二图案，所述第一图案具有由暴露区域包围的未曝光区域，所述第二图案具有 曝光区域，并且通过测量形成在晶片上的第一和第二图案的宽度来检查曝光的聚焦条件。
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公开(公告)号：US20060246359A1
公开(公告)日：2006-11-02
申请号：US11291318
申请日：2005-11-30
申请人： Mika Takahara , Tohru Higashi , Shigehiro Toyoda
发明人： Mika Takahara , Tohru Higashi , Shigehiro Toyoda
CPC分类号： G03F7/70641 , G03F1/44
摘要： There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern having at least one pair of first and second patterns, and the first pattern has an unexposed region surrounded by an exposed region, and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer, the first pattern having an unexposed region surrounded by an exposed region, the second pattern having an exposed region surrounded by an unexposed region, and checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.
摘要翻译： 提供了一种包括晶片和形成在晶片上的聚焦监视图案的半导体器件。 具有至少一对第一和第二图案的焦点监视图案，并且第一图案具有由曝光区域包围的未曝光区域，并且第二图案具有被未曝光区域包围的曝光区域。 另外，本发明提供一种制造半导体器件的方法，包括以下步骤：在晶片上形成至少一对第一和第二图案，所述第一图案具有由暴露区域包围的未曝光区域，所述第二图案具有 曝光区域，并且通过测量形成在晶片上的第一和第二图案的宽度来检查曝光的聚焦条件。
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公开(公告)号：US20060039011A1
公开(公告)日：2006-02-23
申请号：US11244166
申请日：2005-10-06
申请人： Tohru Higashi
发明人： Tohru Higashi
CPC分类号： G03F7/70633
摘要： Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
摘要翻译： 关于组成一批的多个晶片，预先测量这些晶片的对准标记和转印在光致抗蚀剂上的取向图案之间的未对准量，然后，层间电介质膜的厚度和晶片尺寸的值之间的相互关系 被计算。 当实际执行曝光时，首先，在对准标记上大量地形成层间电介质膜并进行平面化。 之后，测量平坦化后的层间电介质膜的厚度。 晶片缩放的值根据批次中的层间电介质膜的厚度的平均值和上述相互关系来估计。 然后，将光致抗蚀剂涂布在批次中的层间电介质膜上，并且在执行校正的同时曝光光致抗蚀剂以补偿晶片缩放的值。
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公开(公告)号：US06979577B2
公开(公告)日：2005-12-27
申请号：US10682299
申请日：2003-10-10
申请人： Tohru Higashi
发明人： Tohru Higashi
CPC分类号： G03F7/70633
摘要： Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
摘要翻译： 关于组成一批的多个晶片，预先测量这些晶片的对准标记和转印在光致抗蚀剂上的取向图案之间的未对准量，然后，层间电介质膜的厚度和晶片尺寸的值之间的相互关系 被计算。 当实际执行曝光时，首先，在对准标记上大量地形成层间电介质膜并进行平面化。 之后，测定平坦化后的层间电介质膜的厚度。 晶片缩放的值根据批次中的层间电介质膜的厚度的平均值和上述相互关系来估计。 然后，将光致抗蚀剂涂布在批次中的层间电介质膜上，并且在执行校正的同时曝光光致抗蚀剂以补偿晶片缩放的值。
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