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公开(公告)号：US5949486A
公开(公告)日：1999-09-07
申请号：US795217
申请日：1997-02-05
申请人： Kazuya Ishihara , Shinichi Uramoto , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami , Shinichi Masuda
发明人： Kazuya Ishihara , Shinichi Uramoto , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami , Shinichi Masuda
IPC分类号： H04N19/50 , H03M7/30 , H03M7/36 , H04N5/14 , H04N19/423 , H04N19/436 , H04N19/51 , H04N7/12
CPC分类号： H04N19/433 , H04N19/51 , H04N5/145
摘要： Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.
摘要翻译： 与模板块和搜索窗口块的像素相对应地布置的每个元素处理器分别包括彼此并行提供的用于存储搜索窗口块像素数据的A寄存器和B寄存器，以及用于存储模板块的T寄存器 像素数据。 通过A和B寄存器中的第一个和存储在T寄存器中的像素数据执行运动矢量评估值计算，而操作数据从A和B中的第一个传送到A和B寄存器中的第二个， B与计算操作并行登记，用于存储下一个搜索窗口的头部搜索窗口块像素数据。 以良好的编码效率高速检测运动矢量。
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2.发明授权Motion vector detecting device capable of accommodating a plurality of predictive modes 失效能够适应多种预测模式的运动矢量检测装置公开(公告)号：US06674798B2
公开(公告)日：2004-01-06
申请号：US09961139
申请日：2001-09-24
申请人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
发明人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
IPC分类号： H04N736
CPC分类号： H04N5/145 , G06T7/223 , G06T7/231 , G06T2207/10016 , H04N19/433 , H04N19/51
摘要： A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode. It is possible to simultaneously detect motion vectors according to a plurality of predictive modes. It is possible to detect motion vectors employed for moving image predictive compensation in accordance with a plurality of predictive modes at a high speed with a small hardware volume.
摘要翻译： 处理器阵列包括对应于作为当前图像像素块的模板块的各个像素的矩阵排列的元件处理器。 每个元素处理器存储作为对应的参考图像像素块的搜索窗口块的像素数据，并获得关于模板块像素数据的评估函数值分量。 求和部分根据多种预测模式对从处理器阵列的相应元件处理器接收的评估函数分量进行排序，并对各种类型的组件求和，以形成各个预测模式的评估函数值。 比较部分比较从每个预测模式的求和部分接收的评估函数值，以确定提供最佳相似度的位移矢量作为每个预测模式的运动矢量。 可以根据多种预测模式同时检测运动矢量。 根据具有小硬件体积的高速的多种预测模式，可以检测用于运动图像预测补偿的运动矢量。
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公开(公告)号：US5394355A
公开(公告)日：1995-02-28
申请号：US109509
申请日：1993-08-20
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。
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公开(公告)号：US5289406A
公开(公告)日：1994-02-22
申请号：US744098
申请日：1991-08-13
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。
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5.发明授权Semiconductor integrated circuit device having a memory and an operational unit integrated therein 失效具有集成在其中的存储器和操作单元的半导体集成电路器件
公开(公告)号：US5379257A
公开(公告)日：1995-01-03
申请号：US767767
申请日：1991-09-30
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C13/00
CPC分类号： G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.
摘要翻译： 半导体集成电路装置包括用于存储要处理的数据的存储单元阵列和用于对从存储单元阵列读取的数据进行预定操作的操作单元。 存储单元阵列具有用于存储第一和第二组的第一和第二数据字的第一和第二区域。 第一数据字和第二数据字各自包括多个数据位。 第一区域包括用于存储第一数据字中相同数位的数据位的多个位阵列，并且第二区域包括用于存储第二数据字中相同数字的数据位的多个位数组。 第一组和第二组的位阵列以数据字的数位顺序交替排列。 存储相同数位数据位的位数组形成一个子阵列。 一个数据字中的数据位存储在位阵列的相同位置。 操作单元包括各自对应于一个子阵列的操作电路。 每个操作电路对从相应子阵列中的两个位阵列读取的数据执行预定的操作。 每个位阵列具有响应于外部地址的选择器，从每个位阵列中选择一个列，并将该列连接到相应的运算电路。
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6.发明授权Output buffer circuit and method of operation thereof with reduced power consumption 失效输出缓冲电路及其降低功耗的操作方法
公开(公告)号：US5204558A
公开(公告)日：1993-04-20
申请号：US760458
申请日：1991-09-17
申请人： Satoshi Kumaki , Shinichi Uramoto
发明人： Satoshi Kumaki , Shinichi Uramoto
IPC分类号： H03K17/687 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/0016
摘要： An output buffer circuit comprises a P channel MOS transistor connected between a power supply terminal and an output terminal, an N channel MOS transistor connected between a ground terminal and an output terminal, a capacitance connected to a ground terminal, and a switch formed of an N channel MOS transistor connected between the output terminal and the capacitance. In charging a load, first, charge stored in the capacitance is supplied to the output terminal, and subsequently the P channel MOS transistor is turned on. In discharging the load, first, charge is supplied from the output terminal to the capacitance, and subsequently the N channel MOS transistor is turned on.
摘要翻译： 输出缓冲电路包括连接在电源端子和输出端子之间的P沟道MOS晶体管，连接在接地端子和输出端子之间的N沟道MOS晶体管，连接到接地端子的电容，以及由 N沟道MOS晶体管连接在输出端子和电容之间。 在对负载充电时，首先，将存储在电容中的电荷提供给输出端，随后P沟道MOS晶体管导通。 在放电负载中，首先从输出端子向电容供电，随后N沟道MOS晶体管导通。
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公开(公告)号：US5375079A
公开(公告)日：1994-12-20
申请号：US009529
申请日：1993-01-27
申请人： Shinichi Uramoto , Kazuya Ishihara
发明人： Shinichi Uramoto , Kazuya Ishihara
CPC分类号： G06F7/5095 , G06F7/544 , G06F2207/5442
摘要： An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N
摘要翻译： 用于增加速度和减小电路尺寸的改进的M位累加器包括N位（N
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公开(公告)号：US5253213A
公开(公告)日：1993-10-12
申请号：US768042
申请日：1991-10-01
CPC分类号： G11C8/04 , G11C7/1006 , G11C8/00
摘要： An SRAM adapted for changing the sequence of data. A counter 7 generates a sequentially increasing address signal. A write designation circuit 2a sequentially designates a memory cell row to be selected for writing in response to the address signal. Conversely, a read designation circuit 3a designates a memory cell row in response to the address signal in a sequence determined by a predetermined rule. The generation of an address signal, which changes in a complicated manner and is required for changing the sequence of data, is not required, so that the amount of the operation process by the CPU is decreased.
摘要翻译： 适用于改变数据序列的SRAM。 计数器7产生顺序增加的地址信号。 写指定电路2a响应于地址信号顺序地指定要被选择的存储单元行。 相反，读取指定电路3a以由预定规则确定的顺序响应于地址信号来指定存储单元行。 不需要生成以复杂的方式改变并且需要改变数据序列的地址信号，所以CPU的操作处理量减少。
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9.发明授权Semiconductor memory device usable as static type memory and read-only memory and operating method therefor 失效半导体存储器件可用作静态存储器和只读存储器及其操作方法
公开(公告)号：US5365475A
公开(公告)日：1994-11-15
申请号：US747204
申请日：1991-08-19
IPC分类号： G11C11/41 , G11C5/14 , G11C11/00 , G11C11/412 , G11C14/00
CPC分类号： G11C5/14 , G11C11/005 , G11C11/412
摘要： Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.
摘要翻译： 半导体存储器件的每个存储单元包括连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，以及连接在节点和节点之间的晶体管。 当制造节点时，每个节点在节目单元中连接到第一电位线和第二电源线中的任一个，并且当节点单元中的每个节点连接到节目单元中的任一个时 被制造。 电源电位被提供给第一电源线，并且电源电位或接地电位被选择性地提供给第二电源线。 接地电位被提供给第一接地线，并且接地电位或供电电势被选择性地提供给第二接地线。
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公开(公告)号：US5303353A
公开(公告)日：1994-04-12
申请号：US862660
申请日：1992-04-01
CPC分类号： G06F13/4018
摘要： A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.
摘要翻译： 数据总线具有2个字的位长度，并被分成两个位组，每个位对应一个字。 因此，数据总线可以同时传输两个字的数据。 寄存器，CPU的数据操作部分，RAM和ROM连接到数据总线。 即使存在要在这些寄存器中传送的两个字的数据，数据操作部分，RAM和ROM，数据总线也可以同时传送数据。 为了防止数据总线上的数据冲突，提供了总线驱动器，多路复用器和总线选择器。
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