公开(公告)号：US5212052A

公开(公告)日：1993-05-18

申请号：US848230

申请日：1992-03-09

申请人： Kei Sakanoue ,  Akira Ogawa

发明人： Kei Sakanoue ,  Akira Ogawa

IPC分类号： G03C7/32 ,  G03C7/36 ,  G03C7/38

CPC分类号： G03C7/365 ,  G03C7/3225 ,  Y10S430/158

摘要： A novel silver halide color photographic material is provided comprising on a support at least one blue-sensitive layer, one green-sensitive layer and one red-sensitive layer, wherein said blue-sensitive layer comprises at least one yellow dye-forming coupler represented by the following general formula (1) and/or (2) and said green-sensitive layer comprises at least one magenta dye-forming coupler represented by the following general formula (M): ##STR1## wherein X.sub.1 and X.sub.2 each represents an alkyl group, an aryl group or a heterocyclic group; X.sub.3 represents an organic residue which forms a nitrogen-containing heterocyclic group together with >N--; Y represents an aryl group or a heterocyclic group; and Z represents a group which separates from the remainder of the molecule when the coupler undergoes a reaction with an oxidation product of a developing agent; ##STR2## wherein R.sub.1 and R.sub.2 each represents a hydrogen atom or a substituent; and X represents a hydrogen atom or a group which separates from the remainder of the molecule when the coupler undergoes a reaction with an oxidation product of a developing agent.

公开(公告)号：US09082469B2

公开(公告)日：2015-07-14

申请号：US13619273

申请日：2012-09-14

申请人： Akira Ogawa ,  Yoshichika Nakaya

发明人： Akira Ogawa ,  Yoshichika Nakaya

IPC分类号： G11C17/16 ,  G11C8/12 ,  G11C7/16 ,  G11C7/20 ,  G11C29/44

CPC分类号： G11C8/12 ,  G11C7/16 ,  G11C7/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor chip D1 of a flash memory which is stacked together with other semiconductor chips D2˜DN to form a multi-chip package (MCP), including a memory cell array 20 of the flash memory for storing an ID code and an upper address, wherein the ID code is written into the a fuse data region 20F of the memory cell array 20 before the assembly process. According to the invention, ID codes and upper addresses can be assigned and written to each of the semiconductor chips of a multi-chip package easily without increasing the size of the semiconductor chips in comparison with the prior art.

摘要翻译： 闪存的半导体芯片D1与其他半导体芯片D2〜DN堆叠以形成多芯片封装（MCP），其包括用于存储ID代码和高地址的闪速存储器的存储单元阵列20， 其中在组装过程之前将ID代码写入存储单元阵列20的熔丝数据区域20F。 根据本发明，与现有技术相比，可以容易地将ID码和上位地址分配并写入多芯片封装的每个半导体芯片，而不增加半导体芯片的尺寸。

公开(公告)号：US08020649B2

公开(公告)日：2011-09-20

申请号：US12160324

申请日：2007-01-11

申请人： Akira Ogawa

发明人： Akira Ogawa

IPC分类号： B62D57/32

CPC分类号： B62D57/032 ,  Y10T74/20329

摘要： A legged robot that ensures a large step length while keeping the height of the trunk low is realized. The legged robot is provided with a trunk, a pair of legs, and a pair of sliding joints. Each of the sliding joints links one end of each of the legs to the trunk so as to slide in a front and rear direction with respect to the trunk. For each step, one leg is caused to slide forward, and the other leg is caused to slide backward. It is possible to ensure a predetermined distance between the end portion of the one leg and the end portion of the other leg. The legged robot can make the step length large by an amount that is equivalent to this distance irrespective of the length of the legs.

摘要翻译： 实现了将腿部高度保持在较低位置的大步长的有腿机器人。 腿式机器人设有躯干，一对腿和一对滑动关节。 每个滑动接头将每个腿的一端连接到躯干，以便相对于躯干在前后方向上滑动。 对于每个步骤，使一条腿向前滑动，另一条腿被向后滑动。 可以确保一条腿的端部和另一条腿的端部之间的预定距离。 腿式机器人可以使步长大到相当于该距离的量，而与腿的长度无关。

公开(公告)号：US20100228173A1

公开(公告)日：2010-09-09

申请号：US12223981

申请日：2006-12-20

申请人： Kiyohito Ishida ,  Kiyoshi Yamauchi ,  Ryosuke Kainuma ,  Yuji Sutou ,  Toshihiro Omori ,  Akira Ogawa

发明人： Kiyohito Ishida ,  Kiyoshi Yamauchi ,  Ryosuke Kainuma ,  Yuji Sutou ,  Toshihiro Omori ,  Akira Ogawa

IPC分类号： A61F5/11 ,  B21D31/00

CPC分类号： A61F5/11

摘要： An elastic metal strip 10 aligning the longitudinal direction with the rolling direction of a cold-rolled plate is collected and processed to a shape comprising a correction plate 16 with the longitudinal direction of the elastic metal 10 as the width direction of nail and a plurality of tongue strips 11 protruded from the edge of the correction plate 16 near the nail tip. The tongue strip 11 is folded and bent to form a hooked claw 17 with a double structure of a folding part 18 and a bending part 19. A nail tip 21 of a deformed nail 20 is inserted between the hooked claw 17 and the correction plate 16 to apply a restoring force of elasticity in the correction plate to the deformed nail 20 as correction ability for deformed nails. A wrought wire rod can be used instead of a cold-rolled plate and a Cu—Al—Mn type shape-memory alloy may further be used as a raw material.

摘要翻译： 将纵向方向与冷轧板的轧制方向对齐的弹性金属带10收集并加工成包括校正板16的形状，弹性金属10的纵向方向作为钉子的宽度方向，多个 从校正板16的靠近钉尖的边缘突出的舌条11。 舌片11被折叠并弯曲以形成具有折叠部分18和弯曲部分19的双重结构的钩爪17.变形指甲20的钉尖21插入在钩爪17和校正板16之间 将校正板中的恢复弹力力作为变形指甲的校正能力施加到变形指甲20。 可以使用锻造线棒代替冷轧板，还可以使用Cu-Al-Mn型形状记忆合金作为原料。

公开(公告)号：US20090285019A1

公开(公告)日：2009-11-19

申请号：US12512638

申请日：2009-07-30

申请人： Akira Ogawa ,  Masaru Yano

发明人： Akira Ogawa ,  Masaru Yano

IPC分类号： G11C16/06 ,  G11C7/06

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压 转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为 在预充电参考单元数据线期间低于预定电压电平。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US07462262B2

公开(公告)日：2008-12-09

申请号：US10919293

申请日：2004-08-17

申请人： Tomomichi Hino ,  Akira Ogawa ,  Shigetoshi Shimauchi ,  Toshihiro Sato ,  Yasuhiro Kabu

发明人： Tomomichi Hino ,  Akira Ogawa ,  Shigetoshi Shimauchi ,  Toshihiro Sato ,  Yasuhiro Kabu

IPC分类号： B01D3/04 ,  F28F9/02 ,  F28D7/16

CPC分类号： F28F9/02 ,  B01D1/06 ,  B01D3/322 ,  F28F9/18

摘要： A vertical multitubular heat exchanger that can prevent clogging of a polymerized material and is continuously operable for an extended period of time is provided. The vertical multitubular heat exchanger (1) of the present invention introduces a process fluid containing an easily-polymerizable substance into heat exchanger tubes (28) to perform heat exchange. The vertical multitubular heat exchanger (1) includes a shell (2) extending in a vertical direction, an upper tube sheet (8) and a lower tube sheet (10) respectively disposed at the upper portion (4) and the lower portion (6) of the shell (2), and a plurality of heat exchanger tubes (28) whose outer circumferences (26) of both ends are respectively fixed to the upper tube sheet (8) and the lower tube sheet (10). An upper surface (34) of the upper tube sheet (8) is formed to be sloped and at least one of the heat exchanger tubes (28) is disposed in the vicinity of the lowest position of the upper surface (34) of the upper tube sheet (8).

摘要翻译： 提供了可以防止聚合材料堵塞并且可延长连续可操作的垂直多管式热交换器。 本发明的立式多管式热交换器（1）将含有易聚合物质的工艺流体引入热交换器管（28）进行热交换。 垂直多管式热交换器（1）包括沿垂直方向延伸的壳体（2），分别设置在上部分（4）和下部分（6）处的上管板（8）和下管板（10） ）和两个外周（26）分别固定在上管板（8）和下管板（10）上的多个热交换器管（28）。 上管板（8）的上表面（34）形成为倾斜的，并且至少一个热交换器管（28）设置在上管（28）的上表面（34）的最下位置附近 管板（8）。

公开(公告)号：US20070180184A1

公开(公告)日：2007-08-02

申请号：US11636111

申请日：2006-12-07

申请人： Mototada Sakashita ,  Masaru Yano ,  Akira Ogawa ,  Tsutomu Nakai

发明人： Mototada Sakashita ,  Masaru Yano ,  Akira Ogawa ,  Tsutomu Nakai

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C2207/2263

摘要： The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.

摘要翻译： 本发明提供一种用于控制具有多个非易失性存储单元的存储单元阵列的半导体器件的半导体器件和方法，该方法包括检测要写入的位数，作为从要编程的数据划分的划分数据 进入存储单元阵列，将比特数与预定比特数进行比较，根据比特数与预定比特数比较的结果，反转或不反相除数数据以产生反转数据，并对 反转数据进入存储单元阵列。 该方法还包括检测要写入的比特数作为下一个分割数据，并将下一个分割数据的比特数与预定比特数进行比较，同时将反演数据编程到存储单元阵列中。

公开(公告)号：US20070002639A1

公开(公告)日：2007-01-04

申请号：US11478554

申请日：2006-06-28

申请人： Akira Ogawa ,  Masaru Yano

发明人： Akira Ogawa ,  Masaru Yano

IPC分类号： G11C5/14

CPC分类号： H01L27/1052 ,  G11C16/0466 ,  G11C16/28 ,  Y10T29/41

摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

摘要翻译： 本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压 转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为 在预充电参考单元数据线期间低于预定电压电平。 根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

公开(公告)号：US20060264668A1

公开(公告)日：2006-11-23

申请号：US10569371

申请日：2004-08-27

申请人： Tomomichi Hino ,  Akira Ogawa

发明人： Tomomichi Hino ,  Akira Ogawa

IPC分类号： C07C51/16 ,  G06F19/00

CPC分类号： C07C51/252 ,  C07C57/04

摘要： The present invention provides a method for producing methacrylic acid through gas-phase catalytic oxidation of methacrolein or a methacrolein-containing gas with molecular oxygen or a gas containing molecular oxygen by the use of a fixed-bed multitubular reactor comprising a plurality of reaction tubes each having a catalyst layer therein, wherein the above catalyst layer is divided in the direction of the tube axis of a reaction tube into two or more layers, to thereby provide a plurality of reaction zones, and the catalyst is caused to be present in the catalyst layer in such a way that a reaction load ratio CRc(i) per unit mass of the catalyst in each reaction zone becomes 0.8 to 1.0.

摘要翻译： 本发明提供了一种通过使用固定床多管反应器通过气相催化氧化甲基丙烯醛或含有异丁烯醛的气体与分子氧或含分子氧的气体来生产甲基丙烯酸的方法，所述固定床多管反应器包括多个反应管 在其中具有催化剂层，其中将上述催化剂层沿反应管的管轴方向分成两层或更多层，从而提供多个反应区，并且催化剂存在于催化剂中 层，使得各反应区域中的催化剂的每单位质量的反应负荷比CRc（i）为0.8〜1.0。

公开(公告)号：US07005430B2

公开(公告)日：2006-02-28

申请号：US10149423

申请日：2000-12-22

申请人： Kimihisa Ueno ,  Akira Ogawa ,  Yoshihisa Ohta ,  Yuji Nomoto ,  Kotaro Takasaki ,  Hideaki Kusaka ,  Hiroshi Yano ,  Chiharu Nakagawa ,  Satoshi Nakanishi

发明人： Kimihisa Ueno ,  Akira Ogawa ,  Yoshihisa Ohta ,  Yuji Nomoto ,  Kotaro Takasaki ,  Hideaki Kusaka ,  Hiroshi Yano ,  Chiharu Nakagawa ,  Satoshi Nakanishi

IPC分类号： C07D487/14 ,  C07D473/24 ,  C07D473/22 ,  A61K31/519 ,  A61P3/10

CPC分类号： C07D487/14

摘要： A condensed purine derivative represented by Formula (I): wherein X—Y-Z represents R1N—C═O or N═C—W, R2 represents a hydrogen atom, a substituted or unsubstituted lower alkyl group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted aryl group, a substituted or unsubstituted aromatic heterocyclic group, a substituted or unsubstituted alicyclic heterocyclic group or the like, n represents an integer of from 0 to 3, V1 represents a hydrogen atom, a substituted or unsubstituted lower alkyl group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted aromatic heterocyclic group, V2 represents a substituted lower alkyl group or a substituted or unsubstituted aromatic heterocyclic group, and when V1 represents a hydrogen atom, a lower alkyl group, a substituted or unsubstituted aralkyl group, or a substituted or unsubstituted aryl group, and for example, X—Y-Z represents R1aN—C═O and R2 represents a substituted lower alkyl group, a substituted or unsubstituted aralkyl group, a substituted or unsubstituted alicyclic heterocyclic group, a halogen atom, a lower alkylthio group, —NR7R8, —CO2H, a lower alkoxycarbonyl group, —COHal, —CONR9R10 or —CHO, V2 may represent a lower alkyl group, a substituted or unsubstituted aralkyl group, or a substituted or unsubstituted aryl group; or a pharmacologically acceptable salt thereof.

摘要翻译： 由式（I）表示的稠合嘌呤衍生物：化学式id =“CHEM-US-00001”num =“000”