公开(公告)号：US06372554B1

公开(公告)日：2002-04-16

申请号：US09390682

申请日：1999-09-07

申请人： Keizo Kawakita ,  Kazuhiko Kajigaya ,  Seiji Narui ,  Kiyoshi Nakai ,  Kazunari Suzuki ,  Hideaki Tsugane ,  Fumiyoshi Sato

发明人： Keizo Kawakita ,  Kazuhiko Kajigaya ,  Seiji Narui ,  Kiyoshi Nakai ,  Kazunari Suzuki ,  Hideaki Tsugane ,  Fumiyoshi Sato

IPC分类号： H01L2182

CPC分类号： H01L27/10894 ,  H01L23/5258 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.

摘要翻译： 覆盖在TEG区域中形成的熔丝的多于一个的导电层的图案经过OR处理; 此外，通过转印技术将连接到所述熔丝的一个或多个测试焊盘的开口图案的组合或“合成”图案复制到涂覆在半导体晶片的表面上的感光性树脂层，从而迫使 树脂层仅驻留在划线区域的选定区域中，合成图案已转移到该区域。

公开(公告)号：US5905685A

公开(公告)日：1999-05-18

申请号：US951734

申请日：1997-10-15

申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

公开(公告)号：US06635918B1

公开(公告)日：2003-10-21

申请号：US09714127

申请日：2000-11-17

申请人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

发明人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.

摘要翻译： 存储单元选择MISFET Q，DRAM的栅电极8A（字线）和位线BL1，BL2的薄层电阻的薄层电阻分别为2Ω/□以下。 在形成栅电极8A（字线WL）或位线BL1，BL2的步骤期间形成外围电路的互连，通过该位线可以减少制造DRAM的步骤的数量。

公开(公告)号：US06201728B1

公开(公告)日：2001-03-13

申请号：US09101009

申请日：1999-02-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

CPC分类号： G11C11/4091 ,  G11C7/065 ,  H01L27/10805

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

摘要翻译： 产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。 第一电压作为其高级侧的工作电压被提供给读出放大器。 产生相对于电路接地电位具有预定差异的第二内部电压。 第二电压作为低电平侧的工作电压提供给读出放大器。 通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。 高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。

公开(公告)号：US06411543B1

公开(公告)日：2002-06-25

申请号：US09755170

申请日：2001-01-08

申请人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

发明人： Seiji Narui ,  Osamu Nagashima ,  Masatoshi Hasegawa ,  Hiroki Fujisawa ,  Shinichi Miyatake ,  Tsuyuki Suzuki ,  Yasunobu Aoki ,  Tsutom Takahashi ,  Kazuhiko Kajigaya

IPC分类号： G11C1124

摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.

公开(公告)号：US06924525B2

公开(公告)日：2005-08-02

申请号：US10642743

申请日：2003-08-19

申请人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

发明人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 Ω/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.

摘要翻译： 存储单元选择MISFET Q，DRAM的栅电极8A（字线）和位线BL 1，BL 2 2的薄层电阻的薄层电阻， 分别为2欧姆/□以下。 在形成栅极电极8A（字线WL）或位线BL SUB1，BL＆lt; 2＆gt; 2的步骤期间形成外围电路的互连，通过该栅极电极 可以减少制造DRAM的步骤。

公开(公告)号：US6150689A

公开(公告)日：2000-11-21

申请号：US782351

申请日：1997-01-13

申请人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

发明人： Seiji Narui ,  Tetsu Udagawa ,  Kazuhiko Kajigaya ,  Makoto Yoshida

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/41

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S257/915

摘要： The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.

摘要翻译： DRAM的存储单元选择MISFET Q的栅电极8A（字线）和位线BL1，BL2的薄层电阻的薄层电阻分别为2Ω/□以下。 在形成栅电极8A（字线WL）或位线BL1，BL2的步骤期间形成外围电路的互连，通过该位线可以减少制造DRAM的步骤的数量。

公开(公告)号：US07397695B2

公开(公告)日：2008-07-08

申请号：US11409097

申请日：2006-04-24

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0076 ,  G11C2213/79

摘要： A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.

摘要翻译： 与DRAM兼容性高的相变存储器。 如果连接到字线WL 0 L的单元MC 0具有低电阻，则流过其的电流高于在虚设单元MR 0中流动的电流，因此位线SA_B处于比其低的电位 的位线SA_T。 该差异由读出放大器SA放大并读出。 在由读出放大器锁存单元数据之前，NMOS晶体管MN 1被截止以将存储单元部分与读出放大器部分断开。 然后，NMOS晶体管MN 10导通，使得所选择的字线上的数据都处于设置状态。 如果要进行写入，则在来自作为I / O线的信号线LIO和RIO的读出放大器SA中进行写入。 但是，在存储单元中不执行写入。 在进行预充电指令以预充电字线WL 0 L之前，NMOS晶体管MN 1再次导通以在单元MC 0中写入复位。

公开(公告)号：US20060211231A1

公开(公告)日：2006-09-21

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L21/3205

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

公开(公告)号：US07449711B2

公开(公告)日：2008-11-11

申请号：US11329224

申请日：2006-01-11

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： H01L47/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

摘要翻译： 相变存储器件包括沿行方向延伸的多个位线，沿列方向延伸的多条选择线，以及各自设置在位线和选择线之间的交叉点之一处的存储单元阵列。 每个存储单元包括串联的硫族化物元件和二极管，以及二极管的n型层下面的n型接触层。 相邻的两个存储单元共享连接n型接触层和位线的公共位线接触插头。