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    Parallel concatenated code with soft-in-soft-out interactive turbo decoder
    2.
    发明授权
    Parallel concatenated code with soft-in-soft-out interactive turbo decoder 失效
    软和软交互式turbo解码器的并行级联代码

    公开(公告)号：US07409006B2

    公开(公告)日：2008-08-05

    申请号：US11481365

    申请日：2006-07-05

    申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

    发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Christopher R. Jones ,  Thomas A. Hughes, Jr.

    IPC分类号： H04L27/00

    CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

    摘要翻译： 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

    Inverse function of min*:min*- (inverse function of max*:max*-)
    3.
    发明授权
    Inverse function of min*:min*- (inverse function of max*:max*-) 有权
    min *的反函数：min * - （最大*的反函数：max * - ）

    公开(公告)号：US07360146B1

    公开(公告)日：2008-04-15

    申请号：US10347732

    申请日：2003-01-21

    申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

    发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Thomas A. Hughes, Jr. ,  Hau Thien Tran

    IPC分类号： H03M13/03

    CPC分类号： H03M13/3905 ,  H03M13/3922 ,  H03M13/395

    摘要： Inverse function of min*:min*− (inverse function of max*:max*−). Two new parameters are employed to provide for much improved decoding processing for codes that involve the determination of a log corrected minimal and/or a log corrected maximal value from among a number of possible values. Examples of some of the codes that may benefit from the improved decoding processing provided by the inverse function of min*:min*− (and/or inverse function of max*:max*−) include turbo coding, parallel concatenated trellis coded modulated (PC-TCM) code, turbo trellis coded modulated (TTCM) code, and low density parity check (LDPC) code among other types of codes. The total number of processing steps employed within the decoding of a signal is significantly reduced be employing the inverse function of min*:min*− (and/or inverse function of max*:max*−) processing.

    摘要翻译： min *的反函数：min * - （max *：max * - 的反函数）。 采用两个新参数来提供对于涉及从多个可能值中确定对数校正的最小值和/或对数校正最大值的代码进行大量改进的解码处理。 可以从由min *：min * - （和/或max *：max * - 的逆函数）提供的改进的解码处理中受益的一些代码的示例包括turbo编码，并行级联网格编码调制（ PC-TCM）码，turbo网格编码调制（TTCM）码和低密度奇偶校验（LDPC）码。 采用min *：min * - （和/或max *：max * - ）的逆函数处理的逆函数，信号解码中采用的处理步骤的总数显着减少。

    Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation)
    4.
    发明授权
    Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) 失效
    非系统和非线性PC-TCM（并行连续网格编码调制）

    公开(公告)号：US07221714B2

    公开(公告)日：2007-05-22

    申请号：US10446318

    申请日：2003-05-27

    申请人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran ,  Christopher R. Jones

    发明人： Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran ,  Christopher R. Jones

    IPC分类号： H04L5/12 ,  H04L23/02

    CPC分类号： H04L1/006 ,  H04L1/0041 ,  H04L1/0066 ,  H04L27/0008 ,  H04L2001/0097

    摘要： Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation). A non-systematic and non-linear PC-TCM code is presented that provides quite comparable performance to turbo encoding using only systematic and linear trellis codes (e.g., convolutional codes). The non-systematic and non-linear PC-TCM described herein may be modified to support a wide variety of code rates (e.g., rate 2/3, 5/6, 8/9, and 3/4 among other rates) and also a wide modulation types (e.g., 8 PSK (8 Phase Shift Key) and 16 QAM (16 Quadrature Amplitude Modulation) among other modulation types). In one embodiment, a non-systematic and non-linear PC-TCM presented herein comes to within approximately 0.15 dB of a systematic and linear turbo code. A design approach is presented that allows for the design of such non-systematic and non-linear PC-TCM codes and several exemplary embodiments are also presented that have been designed according to these presented principles.

    摘要翻译： 非系统和非线性PC-TCM（并行连接网格编码调制）。 提出了一种非系统和非线性PC-TCM代码，其使用仅系统和线性网格码（例如卷积码）提供与turbo编码相当的性能。 本文描述的非系统和非线性PC-TCM可以被修改以支持各种代码率（例如，其他速率中的速率2/3，5/6,8/9和3/4），并且还 宽调制类型（例如，其他调制类型中的8PSK（8相移键）和16QAM（16正交幅度调制））。 在一个实施例中，本文呈现的非系统和非线性PC-TCM在系统和线性turbo码的约0.15dB内。 提出了允许设计这种非系统和非线性PC-TCM代码的设计方法，并且还呈现了根据这些呈现的原理设计的几个示例性实施例。

    Rate control adaptable communications
    5.
    发明授权
    Rate control adaptable communications 有权
    速率控制适应通信

    公开(公告)号：US08898547B2

    公开(公告)日：2014-11-25

    申请号：US12463386

    申请日：2009-05-09

    申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

    发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

    IPC分类号： H03M13/00 ,  H03M13/39 ,  H03M13/29 ,  H03M13/25

    CPC分类号： H03M13/3905 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/6362 ,  H03M13/6516

    摘要： Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.

    摘要翻译： 速率控制适应通信。 在通信系统（编码器和解码器）的两端采用通用网格，以不同速率对数据进行编码和解码。 编码采用单个编码器，其输出位可以被选择性地打孔以支持根据速率控制序列的多个调制（星座和映射）。 单个解码器可操作以解码编码器对数据进行编码的各种速率中的每一个。 速率控制序列可以包括在编码和解码期间重复的周期中布置的速率控制的数量。 编码器和解码器中的一个或两者可以基于包括通信系统的操作条件，信噪比（SNR）等的变化的各种操作参数自适应地选择新的速率控制序列。

    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices
    6.
    发明授权
    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices 有权
    具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码

    公开(公告)号：US08370731B2

    公开(公告)日：2013-02-05

    申请号：US13423381

    申请日：2012-03-19

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    IPC分类号： G06F11/10

    CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

    摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素是0的值）。

    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder
    9.
    发明申请
    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder 有权
    重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器

    公开(公告)号：US20100138721A1

    公开(公告)日：2010-06-03

    申请号：US12651453

    申请日：2010-01-01

    申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/05

    CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

    摘要： Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

    摘要翻译： 重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器。 提出了新的解码方法，通过该方法，立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息，而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息，而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比，使用这种方法，在给定时间段内可以执行两倍的解码迭代，然后更新整个LDPC矩阵的所有位边消息，以及 所以。 当结合最小和处理执行这种重叠方法时，也可以节省大量的内存。

    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    10.
    发明申请
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 失效
    具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码

    公开(公告)号：US20090327847A1

    公开(公告)日：2009-12-31

    申请号：US12533306

    申请日：2009-07-31

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    IPC分类号： G06F11/10

    CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

    摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素为零“0”）。