公开(公告)号：US08174901B2

公开(公告)日：2012-05-08

申请号：US12721553

申请日：2010-03-10

申请人： Ken Matsubara ,  Hideo Kasai ,  Kenji Kawada ,  Makoto Mizuno

发明人： Ken Matsubara ,  Hideo Kasai ,  Kenji Kawada ,  Makoto Mizuno

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C16/06 ,  G11C16/32 ,  G11C16/3418

摘要： This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.

摘要翻译： 本发明是减少存储器栅极驱动器的数量，同时减少以小字节为单位实现写入的存储器阵列配置中的干扰发生次数。 存储器阵列包括多个子阵列，MG传输，SL驱动器和CG驱动器。 每个子阵列包括多个存储器栅极线，控制栅极线，源极线和位线。 存储单元布置在这些线的相交位置。 控制栅极线，CG驱动器，源极线和SL驱动器对于子阵列是共同的，而为每个子阵列提供存储器栅极线和MG缓冲电路。 因此，数据写入的单元减少，并且不增加存储器阵列的电路尺寸的同时降低了干扰的不利影响。

公开(公告)号：US20100232232A1

公开(公告)日：2010-09-16

申请号：US12721553

申请日：2010-03-10

申请人： Ken MATSUBARA ,  Hideo Kasai ,  Kenji Kawada ,  Makoto Mizuno

发明人： Ken MATSUBARA ,  Hideo Kasai ,  Kenji Kawada ,  Makoto Mizuno

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C7/02 ,  G11C16/06 ,  G11C16/32 ,  G11C16/3418

摘要： This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.

摘要翻译： 本发明是减少存储器栅极驱动器的数量，同时减少以小字节为单位实现写入的存储器阵列配置中的干扰发生次数。 存储器阵列包括多个子阵列，MG传输，SL驱动器和CG驱动器。 每个子阵列包括多个存储器栅极线，控制栅极线，源极线和位线。 存储单元布置在这些线的相交位置。 控制栅极线，CG驱动器，源极线和SL驱动器对于子阵列是共同的，而为每个子阵列提供存储器栅极线和MG缓冲电路。 因此，数据写入的单元减少，并且不增加存储器阵列的电路尺寸的同时降低了干扰的不利影响。

公开(公告)号：US07848177B2

公开(公告)日：2010-12-07

申请号：US12269098

申请日：2008-11-12

申请人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

公开(公告)号：US20090129173A1

公开(公告)日：2009-05-21

申请号：US12269098

申请日：2008-11-12

申请人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Shinya KAJIYAMA ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C8/00 ,  G11C7/06

CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行流水线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

公开(公告)号：US08634255B2

公开(公告)日：2014-01-21

申请号：US13181804

申请日：2011-07-13

申请人： Ryotaro Sakurai ,  Hideo Kasai

发明人： Ryotaro Sakurai ,  Hideo Kasai

IPC分类号： G11C7/00 ,  G05F3/02

摘要： Improvement technology of a charge pump circuit is provided for avoiding device destruction due to electrification of an intermediate node of plural capacitors coupled in series to form one step-up capacitor, and avoiding reduction of pump efficiency due to leakage current which flows through a leakage path of the intermediate node concerned. A charge pump circuit includes a step-up capacitor configured by a first capacitance and a second capacitance coupled in series, a capacitance driver, and a protection circuit. The protection circuit is set at a conductive state and discharges a stored charge at the series coupling node of the first capacitance and the second capacitance, when the step-up voltage is not generated, and the protection circuit is maintained in a non-conductive state, when the step-up voltage is generated. Accordingly, relaxation of the withstand voltage of the step-up capacitor is achieved, and reduction of the pump efficiency is avoided.

公开(公告)号：US20090193020A1

公开(公告)日：2009-07-30

申请号：US12418886

申请日：2009-04-06

申请人： Masahiro Kataoka ,  Hiroyuki Torii ,  Masahiro Kurishima ,  Hideo Kasai

发明人： Masahiro Kataoka ,  Hiroyuki Torii ,  Masahiro Kurishima ,  Hideo Kasai

IPC分类号： G06F17/30

CPC分类号： G06F17/30985 ,  G06F17/30911 ,  H03M7/30 ,  Y10S707/99942

摘要： An information retrieval apparatus includes an acquiring unit that acquires a numerical value defining a boundary of a numerical range; a detecting unit that detects a number of places in and a head numeral of the numerical value; an extracting unit that extracts from a bit string group, a bit string indicating whether a numerical value in a numerical value group having the number of places and the head numeral is present in files subject to retrieval; a specifying unit that specifies a file corresponding to a bit in the extracted bit string, the bit indicating the presence of a numerical value of the numerical value group; a determining unit that determines whether a numerical value in the specified file meets the boundary condition; and a designating unit that, based on a determination by the determining unit designates the specified file to have a numerical value within the numerical range.

摘要翻译： 信息检索装置包括获取单元，获取定义数值范围的边界的数值; 检测单元，其检测数字的位置和数字的头数字; 提取单元，从位串组提取表示具有位数的数值组中的数值和头数的位串是否存在于被检索的文件中; 指定单元，其指定与提取的比特串中的比特相对应的文件，表示数值组的数值的存在的比特; 确定单元，确定所述指定文件中的数值是否满足所述边界条件; 以及指定单元，其基于所述确定单元的确定指定所述指定文件以具有所述数值范围内的数值。

公开(公告)号：US20070109900A1

公开(公告)日：2007-05-17

申请号：US11648656

申请日：2007-01-03

申请人： Ryotaro Sakurai ,  Hideo Chigasaki ,  Hideo Kasai

发明人： Ryotaro Sakurai ,  Hideo Chigasaki ,  Hideo Kasai

IPC分类号： G11C11/34 ,  G11C5/14 ,  G11C16/06

CPC分类号： G11C16/30 ,  G11C5/147

摘要： Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.

公开(公告)号：US06888751B2

公开(公告)日：2005-05-03

申请号：US10364342

申请日：2003-02-12

申请人： Kiichi Makuta ,  Akihiro Fujita ,  Hideo Kasai ,  Masashii Wada ,  Atsushi Toukairin

发明人： Kiichi Makuta ,  Akihiro Fujita ,  Hideo Kasai ,  Masashii Wada ,  Atsushi Toukairin

IPC分类号： G01R31/28 ,  G06F12/16 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C29/789

摘要： A nonvolatile semiconductor memory device includes a memory array which comprises a plurality of memory cells of a type wherein predetermined voltages are applied to selected memory cells to change their threshold voltages, whereby information are stored therein according to the difference between the threshold voltages, and whose some memory cells are used as spare memory cells. The nonvolatile semiconductor memory device is provided with a latch circuit connected to each bit line of the memory array through a transmission switch. The memory array is capable of storing therein at least substitutional information for replacing a defective bit by the spare memory cell. The substitutional information is transferred from the memory array to the latch circuit through the transmission switch and held in the latch circuit.

摘要翻译： 非易失性半导体存储器件包括存储器阵列，其包括多种存储单元，其中预定电压被施加到所选择的存储器单元以改变其阈值电压，由此根据阈值电压之间的差异存储信息，并且其中 一些存储单元被用作备用存储单元。 非易失性半导体存储器件设置有通过传输开关连接到存储器阵列的每个位线的锁存电路。 存储器阵列能够至少存储用于由备用存储单元替换缺陷位的替换信息。 替代信息通过传输开关从存储器阵列传送到锁存电路并保持在锁存电路中。

公开(公告)号：US20050041509A1

公开(公告)日：2005-02-24

申请号：US10891297

申请日：2004-07-15

申请人： Chiaki Kumahara ,  Atsushi Shikata ,  Yasuhiro Hakamura ,  Hideo Kasai ,  Hidefumi Odate

发明人： Chiaki Kumahara ,  Atsushi Shikata ,  Yasuhiro Hakamura ,  Hideo Kasai ,  Hidefumi Odate

IPC分类号： G06K19/07 ,  G06F1/00 ,  G06F12/00 ,  G11C16/30 ,  G11C5/14

CPC分类号： G11C16/30

摘要： A memory card and a microcomputer with nonvolatile memory wherein operation under two different types of power supply specifications is achieved are provided. A MultiMediaCard comprises a flash memory and a controller which controls the operation associated with the flash memory. When the controller judges the level of supply voltage supplied from host equipment, it operates as follows: the controller judges whether detecting point corresponding to the voltage level of 1.8V system has been exceeded. After the judgment of excess, the controller judges whether detecting point corresponding to the voltage level of 3.3V system has been exceeded. When the supply voltage is at the voltage level of 1.8V system, the controller causes the flash memory to operate in the 1.8V-system operation mode without driving regulators or level shifters. When the supply voltage is at the voltage level of 3.3V system, the controller drives the regulators and the level shifters to convert the voltage level and causes the flash memory to operate in the 3.3V-system operation mode.

摘要翻译： 提供一种存储卡和具有非易失性存储器的微型计算机，其中实现了两种不同类型的电源规格下的操作。 多媒体卡包括闪存和控制与闪存相关的操作的控制器。 当控制器判断从主机设备供电的电平时，其操作如下：控制器判断是否超过了对应于1.8V系统电压等级的检测点。 超过判定后，控制器判断是否超过与3.3V系统的电压电平对应的检测点。 当电源电压处于1.8V系统的电压电平时，控制器使闪存在1.8V系统运行模式下工作，无需驱动稳压器或电平转换器。 当电源电压处于3.3V系统的电压电平时，控制器驱动稳压器和电平转换器转换电压电平，并使闪存在3.3V系统运行模式下工作。

公开(公告)号：US08478929B2

公开(公告)日：2013-07-02

申请号：US12964803

申请日：2010-12-10

申请人： Yasunobu Aoki ,  Hideo Kasai ,  Masamichi Fujito ,  Junpei Inoue

发明人： Yasunobu Aoki ,  Hideo Kasai ,  Masamichi Fujito ,  Junpei Inoue

IPC分类号： G06F12/00

CPC分类号： G11C7/04 ,  G11C16/22

摘要： To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device.In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.

摘要翻译： 提高在数据处理半导体器件中控制非易失性存储器的重写的可靠性。 在数据处理半导体器件中，控制可重写非易失性存储区域中的数据的读取，写入或擦除的控制单元具有操作模式，其参考输入温度数据来控制数据写入或擦除的温度范围 被执行为比允许读取存储器区域中的数据的温度范围窄。